Lead, Custom Library & Memory Layout (PPA)

NUVACORE; Santa Clara (CA); On-site; USD 180,000 - 240,000; Full time

Job summary

NUVACORE is seeking a Custom Library and Memory Layout Lead to drive layout of advanced CMOS cells and memory arrays. You will own end-to-end layout closure from floorplanning to extraction hand-off and coordinate with circuit, foundry, and CAD teams to optimize PPA and manufacturability.

Responsibilities include defining layout methodologies, building automation for layout generation and LVS/DRC regression, and guiding vendors to deliver high-quality results on tight schedules.

Qualifications

• BS or MS in electrical engineering or related field with strong CMOS layout knowledge.
• 12+ years of custom/standard-cell and/or memory layout experience at advanced nodes.
• Hands-on transistor-level layout experience with latches, flops, and memory arrays.
• Experience with DRC/LVS/antenna, parasitic extraction, and layout-versus-schematic closure.
• Ability to collaborate with foundry, CAD, and circuit design teams on PPA and yield.

Responsibilities

• Lead physical layout of custom library cells and memory arrays at advanced nodes.
• Own end-to-end layout closure: floorplanning, place-and-route, DRC/LVS, and extraction hand-off.
• Define layout methodology and automation and drive P-cell/script-based tooling.
• Manage external layout vendors, set quality/schedule targets, and review deliverables for PPA and compliance.
• Collaborate with circuit design, foundry, and CAD teams to optimize manufacturability and yield.

Skills

Python

Tcl

Education

BS or MS in Electrical Engineering or related field

Tools

Virtuoso

Calibre

StarRC

Job description

NUVACORE is seeking a Custom Library and Memory Layout Lead to drive layout of advanced CMOS cells and memory arrays. You will own end-to-end layout closure from floorplanning to extraction hand-off and coordinate with circuit, foundry, and CAD teams to optimize PPA and manufacturability.

Responsibilities include defining layout methodologies, building automation for layout generation and LVS/DRC regression, and guiding vendors to deliver high-quality results on tight schedules.