Memory & Custom Library Layout Lead — PPA & RTL Integration

NUVACORE; Austin (TX); On-site; USD 180,000 - 260,000; Full time

Job summary

NUVACORE is seeking a Custom Library and Memory Layout Lead to drive the layout of custom cells and memory arrays at advanced CMOS nodes. You will own end-to-end layout closure—from floorplanning to parasitic extraction—and collaborate with circuit design, foundry, CAD, and DFT teams to optimize PPA and manufacturability.

You will define layout methodology, build automation, and manage layout vendors to scale production across macro and cell designs.

Qualifications

• 12+ years in custom/standard-cell and memory layout at advanced CMOS nodes.
• Transistor-level layout experience with latches, flops, and memory arrays.
• Deep knowledge of DRC/LVS/antenna rules and parasitic extraction.
• Hands-on experience with layout-versus-schematic closure using industry tools.

Responsibilities

• Lead end-to-end layout closure including floorplanning, placement, and routing.
• Collaborate with foundry, CAD, and DFT teams to optimize PPA and yield.
• Define layout methodology and automation to raise efficiency.
• Manage layout vendors and review deliverables for compliance.

Skills

Custom layout

Memory layout

Floorplanning

PPA optimization

Scripting (Python/Tcl)

Education

BS/MS in Electrical Engineering

Tools

Virtuoso

Calibre

StarRC

Job description

NUVACORE is seeking a Custom Library and Memory Layout Lead to drive the layout of custom cells and memory arrays at advanced CMOS nodes. You will own end-to-end layout closure—from floorplanning to parasitic extraction—and collaborate with circuit design, foundry, CAD, and DFT teams to optimize PPA and manufacturability.

You will define layout methodology, build automation, and manage layout vendors to scale production across macro and cell designs.