CPU Custom Library Cell Design (IC)

NUVACORE; Austin (TX); On-site; USD 180,000 - 280,000; Full time

Job summary

NUVACORE is building a ground‑up, high performance, low‑power CPU for next‑generation compute workloads. You will design library cells and own IP closure from schematic to layout, interfacing with foundry and CAD teams to optimize PPA on advanced CMOS nodes.

You will contribute to defining flows, automation, and QA processes, while working with DFT and timing models. This senior role requires strong collaboration and deep transistor‑level expertise.

Qualifications

• BS or MS in electrical engineering or related field.
• 12+ years of standard cell and/or memory circuit design experience.
• Hands-on transistor‑level design with latches/FFs and custom logic at advanced CMOS nodes.
• Proficient with industry‑standard EDA tools for schematic, layout, extraction and characterization.
• Experience giving feedback to foundry partners to improve PPA and yield.
• Familiar with STA and Liberty/CCS models for timing/power in Functional and DFT modes.
• Strong communication and collaboration skills with foundry, CAD, and physical design teams.

Responsibilities

• Design and characterize library cells including flip-flops, clock-gating cells, level shifters, and AOI cells to optimize PPA.
• Own end-to-end library IP closure: schematic and layout through DRC/LVS/antenna and characterization.
• Partner with Foundry/PDK, CAD, Physical Design, and DFT teams to benchmark process tech and validate IP on test chips.
• Define and drive adoption of tools, flows, and methodology to raise design efficiency and set team-wide practices.

Skills

Library cells

Transistor‑level design

CDSL/CMOS timing

EDA tool proficiency

STA/Liberty models

Communication & collaboration

Education

BS or MS in Electrical Engineering

Tools

Schematic capture

Layout editors

Parasitic extraction

DC/AC characterization tools

Job description

Nuvacore is building ground-up high performance, low-power CPU for next-generation compute workloads. As a member of the CPU-specific custom circuit design team, you will enable the design to achieve the target PPA specifications for the product.

THE ROLE

• Design and characterize library cells including flip-flops, clock-gating cells, level shifters, and special purpose AOI cells to optimize PPA at advanced process nodes.
• Own end-to-end library IP closure: schematic and layout through DRC/LVS/antenna, parasitic extraction, and characterization
• Partner with Foundry/PDK, CAD, Physical Design, and DFT teams to benchmark new process technology, validate IP on test chips, and co-optimize cells for downstream design PPA.
• Define and drive adoption of Tools, Flows, and Methodology — including characterization automation and compiler QA — to raise design efficiency and set team-wide best practices.

Minimum Qualifications

• Hold a BS or MS degree with (ideally) 12+ years of experience in standard cell and/or custom memory circuit design.
• Hands‑on transistor‑level design experience with static circuits and state‑retaining elements (latches, flops), as well as custom logic gates at advanced CMOS nodes.
• Proficient with industry‑standard EDA tools for schematic, layout, extraction, and characterization, applied to custom cell and memory design workflows.
• Experience providing feedback to foundry partners to help improve PPA, yield, and other important qualities in future revisions of the PDK.
• Well‑versed in STA and Liberty/CCS model correlation, including timing and power characterization for both Functional and DFT (Design for Test) modes.
• Strong communication and collaboration skills, comfortable working directly with foundry, CAD, and physical design partner teams.

Requirements — Preferred

• Experience across the full design flow of a custom circuit — cell/memory architecture, circuit design, compiler automation, characterization, and timing/model generation.
• Experience translating PDK device characteristics into circuit decisions.
• Proven PPA-focused execution for standard cells, including architecture trade‑offs, critical‑path modeling, full‑cut analysis, and Monte Carlo variation studies.
• Experience using Agentic AI tools for productivity and automation.

We may use artificial intelligence (AI) tools to support parts of the hiring process, such as reviewing applications, analyzing resumes, or assessing responses and identifying potential inconsistencies or verification signals in application materials based on available information. These tools assist our recruitment team but do not replace human judgment. Final hiring decisions are ultimately made by humans. If you would like more information about how your data is processed, please contact us.