CPU CDC/RDC/STA Engineer

Apple Inc.; Santa Clara (CA); On-site; USD 180,000 - 240,000; Full time

Job summary

Apple Inc. in Santa Clara is seeking a senior hardware verification engineer to own the CDC/RDC sign-offs for CPU designs, collaborate with RTL and DV teams, and drive robust STA checks across multi-clock domains.

The role requires deep Verilog/SystemVerilog expertise, experience with CDC/RDC, EDA tools such as Synopsys or Real Intent, TCL/Perl scripting, and a track record of delivering safe, scalable designs in complex SoC environments.

Qualifications

• Minimum BS and 10+ years of relevant industry experience.
• Experience with Clock-Domain Crossing (CDC) and Reset Domain Crossing (RDC).
• Experience with at least one of the following: Synopsys or Real Intent tool.
• Scripting experience in TCL or Perl.
• Experience in Verilog.

Responsibilities

• Develop, improve, and maintain CDC and RDC sign-offs for CPU designs.
• Collaborate with RTL and DV teams to specify SystemVerilog assertions for CDC/RDC/STA constraints.

Skills

CDC

RDC

Verilog

SystemVerilog

SVA (SystemVerilog Assertions)

TCL

Perl

EDA tools (Synopsys/Real Intent)

Spyglass/PrimeTime/Meridian

Education

BS in Electrical Engineering or related field

Tools

Synopsys tools

Real Intent tools

Spyglass

PrimeTime

Meridian

Job description

Imagine what you could do here. At Apple, new ideas have a way of becoming extraordinary products, services, and customer experiences very quickly. Bring passion and dedication to your job and there's no telling what you could accomplish. Dynamic, intelligent people and inspiring, innovative technologies are the norm here. The people who work here have reinvented entire industries with all Apple Hardware products. The same passion for innovation that goes into our products also applies to our practices strengthening our commitment to leave the world better than we found it. Do you want to join us in these pursuits? Join us to help deliver the next groundbreaking Apple product!

Description

In this role, you will be:

• Responsible for developing, improving, and maintaining the CDC and RDC sign-offs for CPU designs
• Working with RTL and DV teams to recommend System Verilog assertions needed to support CDC/RDC/STA constraints and assumptions
• Highlighting to the RTL team any CDC/RDC issues and recommending solutions to them and educating them on CDC/RDC issues and the importance of structurally safe solutions to each issue
• Responsible for developing, enhancing, and maintaining key STA checks and associated sign-offs for our CPUs including things needed to complement CDC/RDC
• Responsible for debugging vendor tool problems and collaborate with designers to help solve their problems
• Working closely with EDA vendor representatives to drive improvements and new methodologies
• Working closely with RTL, Verification, CAD, and Physical Design teams

Minimum Qualifications

• Minimum BS and 10+ years of relevant industry experience
• Experience with Clock-Domain Crossing (CDC) and Reset Domain Crossing (RDC)
• Experience with at least one of the following: Synopsys or Real Intent tool
• Scripting experience in TCL or Perl
• Experience in Verilog

Preferred Qualifications

• Experience in SystemVerilog Assertions (SVA) and Design Verification (DV) Simulations
• Experience in multi-clock-domain RTL design
• Knowledge in Spyglass, VC-Static, PrimeTime, or Meridian is a plus

Apple is an equal opportunity employer that is committed to inclusion and diversity. We seek to promote equal opportunity for all applicants without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, Veteran status, or other legally protected characteristics. Learn more about your EEO rights as an applicant

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Apple accepts applications to this posting on an ongoing basis.