Senior CPU Architecture & Performance Engineer (Data Center & AI)

Samsung Semiconductor; San Jose (CA); On-site; USD 138,000 - 206,000; Full time

Job summary

Samsung Semiconductor in San Jose is seeking a Senior Engineer for Architecture & Performance Research focused on data center and agentic AI CPU work. You will drive microarchitectural research, performance modeling, and collaborate with RTL teams from modeling to silicon validation.

You will analyze workloads, run simulations, and identify opportunities to improve IPC, CPI, latency and throughput, while exploring AI‑driven design methods.

Qualifications

• Master’s degree in Computer Architecture, Computer Engineering, or a related field.
• 3+ years in Computer Architecture or performance engineering; PhD acceptable.
• 1+ years of experience in CPU microarchitecture or performance engineering.
• Strong understanding of out-of-order execution, branch prediction, pipelines, and memory systems.
• Hands-on experience with architectural simulators such as gem5.
• Proficiency in C/C++ and Python.

Responsibilities

• Collaborate with Staff and Principal Engineers to own a microarchitectural domain from idea to validation.
• Participate in design implementation and validation using AI-driven design methodologies.
• Run architectural simulations and performance models; analyze IPC, CPI stacks, latency, throughput.
• Identify performance bottlenecks and optimization opportunities across the front-end, mid-end, and back-end.
• Characterize workloads and benchmarks to understand performance behavior.
• Develop scripts and tools to automate and accelerate performance analysis and exploration.
• Contribute to patents and technical publications.

Skills

CPU architecture

Performance engineering

C/C++

Python

Education

Master’s in Computer Architecture or related field

Tools

gem5

Job description

Samsung Semiconductor in San Jose is seeking a Senior Engineer for Architecture & Performance Research focused on data center and agentic AI CPU work. You will drive microarchitectural research, performance modeling, and collaborate with RTL teams from modeling to silicon validation.

You will analyze workloads, run simulations, and identify opportunities to improve IPC, CPI, latency and throughput, while exploring AI‑driven design methods.