Principal CPU Architect - RISC-V & Performance

Samsung Semiconductor Inc.

San Jose (CA)

On-site

USD 219,000 - 351,000

Full time

14 days+
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Benefits offered by this job

4+ weeks paid time off
Fertility/adoption support
Onsite cafe and gym
Flexible work environment

Job summary

Samsung Semiconductor, Inc. seeks a Principal CPU Architecture & Performance Engineer to define the architectural vision for next-generation CPU platforms and agentic AI workloads. You will identify opportunities, develop performance models, and drive microarchitectural concepts across multiple domains.

Close collaboration with RTL teams will translate ideas into silicon. You will mentor senior engineers and contribute to patents and publications, shaping architecture across generations while

Qualifications

  • Master's degree with 18+ years of experience or PhD with 15+ years.
  • Extensive CPU microarchitecture and research experience.
  • Proficient in C/C++ and Python; performance analysis tools.

Responsibilities

  • Define architectural vision for next-gen CPU platforms and workloads.
  • Identify opportunities across emerging workloads and shapes long-term design direction.
  • Collaborate with RTL/design teams to translate architecture into silicon.
  • Mentor Senior and Staff engineers and drive research outputs and patents.

Skills

CPU microarchitecture
Performance modeling
C/C++ and Python
gem5 & RTL collaboration
Mentoring senior engineers

Education

Master's in Computer Engineering/CS
PhD (preferred) in related field

Tools

gem5

Job description

Samsung Semiconductor, Inc. seeks a Principal CPU Architecture & Performance Engineer to define the architectural vision for next-generation CPU platforms and agentic AI workloads. You will identify opportunities, develop performance models, and drive microarchitectural concepts across multiple domains.

Close collaboration with RTL teams will translate ideas into silicon. You will mentor senior engineers and contribute to patents and publications, shaping architecture across generations while

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