Chip Lead / Physical Design Director

Cadence Design Systems; Austin (TX); On-site; USD 180,000 - 240,000; Full time

Job summary

Cadence Design Systems in Austin, TX is seeking a highly experienced Physical Design Architect/Chip Lead to drive RTL-to-GDS efforts for SoCs in data centers, automotive, and AI domains.

You will lead a PD team, influence sign-off criteria, and collaborate with customers to meet PPAS targets. 15+ years in PD with extensive EDA tool experience, especially Genus, Innovus, and PrimeTime, are expected.

Qualifications

• Have 15+ years in Physical Design or equivalent.
• Bachelor’s in CS/Engineering or related field.
• Strong fundamentals in digital design and semiconductor concepts.
• Experience with IC digital implementation flows and backend EDA tools.
• Proven design-closure experience for chip top-level projects.

Responsibilities

• Lead Physical Design and DFT teams from RTL/Netlist to GDS.
• Drive PPAS optimization and meet aggressive design schedules.
• Guide foundry/node selection and memory/compiler choices.
• Collaborate with Cadence tool R&D to improve methodologies.
• Share best practices and lessons learned across programs.

Skills

Digital Design

Semiconductor fundamentals

RTL-to-GDS flow

Scripting: Tcl/Perl/Python

Customer-facing communication

Education

Bachelor’s degree in CS/Engineering

Master’s degree preferred

Tools

Genus

Innovus

Conformal

Tempus

Modus

Voltus

ICC/ICC2

PrimeTime

Job description

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. We are excited to welcome highly talented Physical Design Architects and Chip Leads to join our Cadence Performance Solutions Group (PSG). Working at Cadence means collaborating with some of the industry’s brightest minds and driving innovation for the world’s most advanced companies. Through Cadence’s tools, emulation hardware, and IP products, we have supported a diverse range of customers. Enabling products in data centers, advanced driver-assistance system (ADAS) automotive and physical AI, and cutting-edge artificial intelligence verticals. As an expert Physical Design Architect, you will engage directly with our leading-edge customers to deliver differentiated RTL-to-GDS services in advanced FinFET nodes. You will lead a talented Physical Design team with the goal of not only meeting but exceeding customers’ demanding Performance, Power, Area, and Schedule (PPAS) targets. At Cadence, our customers are at the heart of everything we do, and talented leaders like you are essential to turning this passion into tangible results.

Key Responsibilities

Serve as the technical leader for Physical Design and Design for Test teams, driving complex customer SoC projects from RTL or Netlist to GDS. These critical SoCs are targeted for markets such as data centers, automotive, and artificial intelligence. Work directly with customers throughout engagements, from initiation to final GDS delivery, taking ownership of technical decisions, design trade-offs, and innovative problem solving to achieve customer PPA and schedule requirements. Guide customers in selecting the appropriate foundry/node, library, and memory compiler, and establish sign-off criteria to ensure the best features versus cost trade-offs. Collaborate with internal Cadence teams to deliver technical presentations and promote internal AI initiatives to improve quality and efficiency. Work closely with customer or internal RTL/Synthesis teams to ensure that key metrics are achieved efficiently prior to the physical design execution phase gate. Partner with Cadence tools R&D to enhance tools and methodologies to meet and surpass customer requirements. Document and share best practices and lessons learned from ongoing and completed projects to improve efficiency, success rates, and AI adoption in future programs.

Job Requirements

• Fifteen or more years of industry experience in Physical Design.
• Bachelor’s degree in Computer Science/Engineering, Electrical Engineering, or a related field.
• Strong knowledge of Digital Design Fundamentals, Semiconductor fundamentals, and Static Timing Analysis (including timing constraints).
• Experience with IC digital implementation flows and backend EDA tools, including Place and Route, Clock Tree Synthesis, IR Drop analysis, backend design timing, and power closure.
• Demonstrated experience in complete design closure for chip top-level projects.
• Expertise in PPA optimization, including driving trade-offs between performance, power, and area to meet aggressive design requirements.
• Experience with advanced nodes at 7nm and below.
• Proficiency in scripting languages such as Tcl, Perl, or Python is essential.
• Strong customer-facing communication and problem-solving skills.
• Personal drive for continuous learning and expanding professional skill sets.
• Experience in building strong technical relationships with internal stakeholders, including RTL, DFT, CAD, and Library teams.

Preferred Qualifications

• Master’s degree in Computer Science/Engineering, Electrical Engineering, or a related field.
• Prior experience with IC digital implementation flows and front-end EDA tools, including Synthesis, DFT, and Logical Equivalence Checking.
• Experience with Cadence tools such as Genus, Innovus, Conformal, Tempus, Modus, Voltus, or with similar tools like ICC, ICC2, DC, or Primetime is highly desired.
• Experience with advanced nodes at 5nm and below.
• Domain expertise in CPUs, GPUs, AI Engines, Networks on Chip (NoCs), or high-speed interfaces.
• Experience with 3D IC design is a significant plus.

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