Senior Cache-Coherent Interconnect Architect (2.5D/3D)

NVIDIA Corporation; United States; On-site; USD 168,000 - 311,000; Full time

Benefits offered by this job

Equity

Benefits

Job summary

NVIDIA Corporation is seeking a Senior Logic Design Engineer to lead silicon architecture and construction of next-generation CPU processors. You will explore dielet packaging options and plan die-to-die IO, collaborating across architecture, logic design, physical design, and packaging teams to achieve target area, performance and power goals.

You will work on 2D/2.5D/3D integration, UCIe, DRAM and PCIe interfaces, while leveraging expertise in cache coherency and high-speed interconnects.

Qualifications

• Master’s Degree in Electrical Engineering, Computer Engineering or CS.
• 8+ years of processor/semiconductor design experience.
• Deep knowledge of digital design and CPU architecture.
• Strong background in cache coherency or high-speed interconnects.
• Experience with advanced packaging (TSMC InFO/CoWoS, Intel EMIB) preferred.

Responsibilities

• Own the silicon architecture and construction plan for next-generation CPU processors.
• Explore 2D/2.5D/3D dielet constructions and IO placement across dielets.
• Plan die-to-die and off-chip IO, including UCIe, DRAM and PCIe.
• Collaborate with architecture, logic design, physical design and packaging teams to meet area, performance, power and thermal goals.

Skills

Cache coherency

Digital design

CPU architecture

ASIC floorplanning

Interconnects

Communication skills

Education

Master's degree in EE/CE/CS

Job description

NVIDIA Corporation is seeking a Senior Logic Design Engineer to lead silicon architecture and construction of next-generation CPU processors. You will explore dielet packaging options and plan die-to-die IO, collaborating across architecture, logic design, physical design, and packaging teams to achieve target area, performance and power goals.

You will work on 2D/2.5D/3D integration, UCIe, DRAM and PCIe interfaces, while leveraging expertise in cache coherency and high-speed interconnects.