Senior Silicon Architect - Cache Coherent Interconnects

NVIDIA Corporation; Santa Clara (CA); Sur place; USD 168 000 - 311 000; Plein temps

Avantages offerts par ce poste

Equity benefits

Résumé du poste

NVIDIA Corporation in Santa Clara, CA seeks a Senior Logic Design Engineer to drive silicon architecture for next‑gen CPU processors. You will explore dielet partitioning, 2.5D interposers, and die-to-die interfaces, coordinating with architecture, physical design, and packaging teams to meet area, performance, and power goals.

The role requires a Master’s in EE/CE/CS, 8+ years in high‑performance semiconductor design, and deep knowledge of digital design and cache coherency.

Qualifications

• Master’s Degree in Electrical Engineering, Computer Engineering or Computer Science or equivalent experience.
• 8+ years of experience in processor or other related high-performance semiconductor designs.
• Deep understanding of digital design, CPU system architecture and ASIC floor-planning.
• Strong background in cache coherency or high-speed interconnects and industry-standard coherency/IO/memory protocols is helpful.
• Knowledge of advanced packaging (TSMC InFO and CoWoS, Intel EMIB), through-silicon via configurations and backside power delivery is preferred, along with Dielet, Interposer, Substrate connectivity.

Responsabilités

• Own the silicon architecture and construction plan for next-generation CPU processors.
• Explore 2D multi-chip module, 2.5D interposer and 3D hybrid-bonded dielet constructions, including IO and compute placement.
• Plan die-to-die and off-chip IO, including UCIe, DRAM and PCIe.
• Work with architecture, logic design, physical design and packaging teams to meet area, performance, power and thermal goals.

Connaissances

Digital design

CPU architecture

ASIC floor-planning

Cache coherency

Interconnects

Dielet & interposer

Formation

Master’s Degree in EE/CE/CS

Description du poste

We are now looking for a Senior Logic Design Engineer! As a member of our CPU Cache Coherent Interconnects Design Team, you will be responsible for the silicon architecture and construction of our CPU processors, focusing on such tasks as dielet partitioning, packaging and die-stacking exploration, floorplanning and die-to-die interface planning. This position offers you the opportunity to have real impact in a dynamic, technology-focused company impacting product lines ranging from consumer graphics to self-driving cars and the growing field of artificial intelligence! We have crafted a team of extraordinary people stretching around the globe, whose mission is to push the frontiers of what is possible today and define the platform for the future of computing. NVIDIA is widely considered to be one of the technology world’s most desirable employers. We have some of the most brilliant and hardworking people in the world working for us. Are you creative and autonomous? Do you love the challenge of crafting the fastest and most power-efficient chips in their class? If so, we want to hear from you.

What you'll be doing:

As a member of our core CPU team, you'll own the silicon architecture and construction plan for next-generation CPU processors. Explore 2D multi-chip module, 2.5D interposer and 3D hybrid-bonded dielet constructions, including the placement of IO and compute (CPU cores, caches and NOC) across dielets. Develop early floorplans, and plan die-to-die and off-chip IO, including UCIe, DRAM and PCIe. Work with architecture, logic design, physical design and packaging teams to achieve your area, performance, power and thermal goals.

What we need to see:

• Master’s Degree in Electrical Engineering, Computer Engineering or Computer Science or equivalent experience.
• 8+ years of experience in processor or other related high-performance semiconductor designs.
• Deep understanding of digital design, CPU system architecture and ASIC floor-planning, including wire densities on-die and across 3D connected dies.
• A strong background in cache coherency or high-speed interconnects and industry-standard coherency/IO/memory protocols is helpful.
• Knowledge of advanced packaging (TSMC InFO and CoWoS, Intel EMIB), through-silicon via configurations and backside power delivery is preferred, along with Dielet, Interposer, Substrate connectivity.
• Strong communication and interpersonal skills are required along with the ability to work in a dynamic, global team.

Your base salary will be determined based on your location, experience, and other objective job-related factors.

The expected base salary ranges for this position are: 168,000 USD – 264,500 USD for Level 4; and 196,000 USD – 310,500 USD for Level 5.

Benefits:

• You will also be eligible for equity and benefits.

Applications for this job will be accepted at least until November 3, 2026.

This posting is for an existing vacancy.

NVIDIA uses AI tools in its recruiting processes.

NVIDIA is committed to fostering an inclusive work environment and proud to be an equal opportunity employer.

As we highly value diversity in our current and future employees, we do not discriminate (including in our hiring and promotion practices) on the basis of race, religion, color, national origin, gender, gender expression, sexual orientation, age, marital status, veteran status, disability status or any other characteristic protected by law.

NVIDIA pioneered accelerated computing. Today, our AI infrastructure powers global intelligence, transforming every industry.

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