Senior ATE Test Infrastructure Engineer for TPU & HPC

Google LLC; Sunnyvale (CA); On-site; USD 163,000 - 236,000; Full time

Job summary

Google LLC in Sunnyvale, CA is hiring an SoC Test Infrastructure Engineer to shape the future of AI/ML hardware acceleration. You will drive post-silicon NPI and high-volume test strategies for TPU and HPC products, crafting and validating ATE programs and pre-silicon test solutions for cutting-edge silicon.

Expect collaboration across architecture, design, and verification to optimize silicon testing life-cycle.

Qualifications

• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
• 8 years of experience in test engineering.
• Experience scripting in Python or Java.
• Experience with ATE test platforms such as Advantest 93K, Teradyne UltraFlex SOC test system.

Responsibilities

• Develop and validate test programs on Automated Test Equipment (ATE) platforms for new product integration (NPI) and high-volume manufacturing (HVM).
• Verify test solutions on pre-silicon models and develop ATE test modules, DC tests, binning, production, and characterization flows.
• Build tools, flows, and methodologies to automate the testing life-cycle.
• Collaborate with Architecture, Design, and Verification teams to develop manufacturing test strategies for HPC products.
• Partner with upstream and downstream teams to enable automated test solutions.

Skills

Test engineering

Python

Java

C/C++

Education

Bachelor's degree in EE/CE/CS

Master's or PhD in EE/CS with focus on computer architecture

Tools

Advantest 93K

Teradyne UltraFlex SOC

Job description

Google LLC in Sunnyvale, CA is hiring an SoC Test Infrastructure Engineer to shape the future of AI/ML hardware acceleration. You will drive post-silicon NPI and high-volume test strategies for TPU and HPC products, crafting and validating ATE programs and pre-silicon test solutions for cutting-edge silicon.

Expect collaboration across architecture, design, and verification to optimize silicon testing life-cycle.