Senior ATE Test Engineer – SoC & High‑Speed Protocols

Asteralabs; San Jose (CA); On-site; USD 136,000 - 170,000; Full time

Job summary

Astra Labs is seeking a Senior ATE Test Engineer to lead SoC test strategies for high-volume mixed-signal silicon products. You will define ATE programs, work with manufacturing partners, and own the product from design to ramp.

You should have 2+ years releasing SoC silicon to high-volume manufacturing, hands-on experience with PCIe/Ethernet/Infiniband/DDR/NVMe/USB, and strong programming skills in C/C++ or Python. Remote options not specified.

Qualifications

• Bachelor’s in EE at minimum; Master’s preferred.
• ≥2 years releasing complex SoC/silicon to high-volume manufacturing.
• Experience with PCIe/Ethernet/Infiniband/DDR/NVMe/USB protocols.
• Strong teamwork and communication abilities.
• DFT knowledge: SCAN, MEMBIST, SerDes.
• Proficiency in C/C++, Python.

Responsibilities

• Develop and oversee SoC test strategy and ATE programs.
• Interact with manufacturing partners and define, own, test plans.
• Lead product from design through initial samples to high-volume ramp.
• Collaborate with design teams to optimize test coverage.

Skills

C/C++

Python

High-speed protocols

Test engineering

DFT techniques

Education

Bachelor's in Electrical Engineering

Master's degree preferred

Tools

Advantest 93k ATE

High-speed test platforms

Protocol analyzers

Oscilloscopes

Job description

Astra Labs is seeking a Senior ATE Test Engineer to lead SoC test strategies for high-volume mixed-signal silicon products. You will define ATE programs, work with manufacturing partners, and own the product from design to ramp.

You should have 2+ years releasing SoC silicon to high-volume manufacturing, hands-on experience with PCIe/Ethernet/Infiniband/DDR/NVMe/USB, and strong programming skills in C/C++ or Python. Remote options not specified.