ATE Test Engineer

iFlow Inc.; Mountain View (CA); On-site; USD 100,000 - 130,000; Full time

Job summary

iFlow Inc. is seeking a highly skilled professional to develop and debug ATE test programs for IP and SoC devices in Mountain View, CA. The role requires 10-15 years of experience in digital test methodologies and hands-on experience with ATE platforms like Advantest 93K or SMT8.

The ideal candidate will also be involved in executing functional tests and collaborating with engineering teams. A Bachelor's or Master's degree in Electrical/Electronics Engineering is required.

Qualifications

• Hands-on experience with ATE platforms such as Advantest 93K or SMT8.
• Strong background in digital test methodologies.
• Experience with HSIO, DDR, or similar high-speed interfaces.

Responsibilities

• Develop and debug ATE test programs for IP and SoC devices.
• Perform IP-level characterization and validation.
• Execute functional tests including HSIO, DDR, and vector-based testing.

Skills

ATE platforms experience

Digital test methodologies

Experience with HSIO

Vector translation familiarity

Education

Bachelor's or Master's in Electrical/Electronics Engineering

Tools

Advantest 93K

SMT8

Job description

Location: Mountain View, CA - On-site work

Duration: Full-time Only

Experience: 10-15 Years

Key Responsibilities

• Develop and debug ATE test programs for IP and SoC devices.
• Perform IP-level characterization and validation.
• Execute functional tests including HSIO, DDR, and vector-based testing.
• Work on SMT8/93K or similar ATE platforms.
• Support translation of functional models into production test vectors.
• Collaborate with design, DV, and product engineering teams.
• Perform debugging, failure analysis, and test optimization.
• Contribute to Digital and AMS block testing.

Required Qualifications

• Hands‑on experience with ATE platforms (e.g., Advantest 93K, SMT8).
• Strong background in digital test methodologies.
• Experience with HSIO, DDR, or similar high‑speed interfaces.
• Familiarity with vector translation and functional model testing.
• Bachelor s or Master s degree in Electrical/Electronics Engineering.

Preferred

• Experience with mixed‑signal (AMS) testing.
• Exposure to IP-level or SoC characterization flows.