Senior ASIC Verification Engineer – SystemVerilog/UVM Expert

MaC VC; San Diego (CA); On-site; USD 122,000 - 183,000; Full time

Job summary

Qualcomm Technologies, Inc. in San Diego, CA seeks a verification engineer to lead pre-silicon test planning for digital power IPs, develop testbenches with SystemVerilog/UVM, and build coverage and assertion models.

The role emphasizes formal verification techniques and automation to raise verification efficiency. The candidate should have strong ASIC design/verification experience and a background in SystemVerilog and related methodologies.

Qualifications

• Bachelor's degree in Engineering, Science, or a closely related field.
• 2+ years of experience with ASIC design and verification tools, techniques, and methodology.

Responsibilities

• Lead pre-silicon test planning for digital power IPs and develop testbenches using SystemVerilog-UVM.
• Develop coverage, assertion models, and formal verification (property checking).
• Involve in automation to improve verification efficiency.

Skills

ASIC design

SystemVerilog/Verilog

C/C++ programming

UVM/OVM verification

Perl or Python scripting

Education

Bachelor’s degree in Science/Engineering

Master’s degree in Science/Engineering

PhD in Science/Engineering

Tools

AMBA AXI/AHB/APB

Job description

Qualcomm Technologies, Inc. in San Diego, CA seeks a verification engineer to lead pre-silicon test planning for digital power IPs, develop testbenches with SystemVerilog/UVM, and build coverage and assertion models.

The role emphasizes formal verification techniques and automation to raise verification efficiency. The candidate should have strong ASIC design/verification experience and a background in SystemVerilog and related methodologies.