Senior ASIC Verification Engineer — SystemVerilog/UVM (CRD)

Broadcom; Broomfield (CO); On-site; USD 129,000 - 207,000; Full time

Benefits offered by this job

Medical, dental and vision plans

401(k) with company matching

Employee Stock Purchase Program (ESPP)

Paid holidays and vacation

Job summary

Broadcom in Colorado is seeking a highly skilled Constrained Random Design Verification Engineer to join a stable team developing silicon products for Ethernet systems in the cloud. You will verify new designs that evolve rapidly using SystemVerilog and UVM, with opportunities for technical leadership and global collaboration.

The role requires 12+ years of related experience (or advanced degrees with relevant experience) and a strong background in verification methodologies, OOP, and scripting.

Qualifications

• Strong experience in constrained random verification methodologies.
• Proficiency with SystemVerilog and UVM.
• Ability to drive coverage closure to completion.
• Experience mentoring others in verification teams.

Responsibilities

• Verify designs using SystemVerilog/UVM across multiple IPs.
• Lead verification efforts and technical leadership.
• Collaborate with design and architecture teams worldwide.
• Develop verification plans and coverage metrics.

Skills

Constrained random verification

SystemVerilog

UVM

OOP

Team collaboration

Education

Bachelor's degree

Master's degree

PhD

Tools

VCS

Incisive

Python

Perl

Job description

Broadcom in Colorado is seeking a highly skilled Constrained Random Design Verification Engineer to join a stable team developing silicon products for Ethernet systems in the cloud. You will verify new designs that evolve rapidly using SystemVerilog and UVM, with opportunities for technical leadership and global collaboration.

The role requires 12+ years of related experience (or advanced degrees with relevant experience) and a strong background in verification methodologies, OOP, and scripting.