Senior ASIC Verification Engineer - SystemVerilog/UVM

Xforia Global Talent & Technology Solutions; Austin (TX); On-site; USD 108,000 - 132,000; Full time

Job summary

Xforia Global Talent & Technology Solutions in Austin, TX, is seeking an experienced ASIC Design Verification Engineer to join our silicon engineering team. You will develop and execute SystemVerilog/UVM based verification plans for complex IPs or SoCs and drive coverage closure.

The role emphasizes constrained-random test generation, regression debugging, and close collaboration with RTL designers to resolve RTL issues and meet project milestones.

Qualifications

• Bachelor's or Master’s degree in Electrical Engineering, Computer Engineering, or related field.
• 5+ years of experience in ASIC/SoC Design Verification.
• Strong SystemVerilog and UVM expertise.
• Experience with constrained-random verification and coverage-driven methodologies.
• Strong debugging using waveform and simulation tools.
• Experience developing assertions (SVA) and functional coverage.
• Familiarity with version control systems and Linux development environments.

Responsibilities

• Develop directed and constrained-random test cases to verify functionality and corner cases.
• Perform regression debugging and root-cause analysis of RTL and testbench failures.
• Drive functional and code coverage closure to meet project milestones.
• Collaborate closely with RTL designers to resolve the design issues.

Skills

SystemVerilog

UVM

Constrained-random verification

Coverage-driven verification

Debugging

Assertions (SVA)

Version control

Linux

Education

Electrical/Computer Engineering degree

Tools

Waveform tools

Simulation tools

Git

Job description

Xforia Global Talent & Technology Solutions in Austin, TX, is seeking an experienced ASIC Design Verification Engineer to join our silicon engineering team. You will develop and execute SystemVerilog/UVM based verification plans for complex IPs or SoCs and drive coverage closure.

The role emphasizes constrained-random test generation, regression debugging, and close collaboration with RTL designers to resolve RTL issues and meet project milestones.