Senior ASIC Verification Engineer — RSU Eligible

QUALCOMM, Inc.; Santa Clara (CA); Sur place; USD 190 000 - 285 000; Plein temps

Résumé du poste

Qualcomm Technologies, Inc. is seeking a Hardware Engineer to plan, design, verify, and test complex SOC-level hardware and RF/analog systems, bringing up yield, packaging, and test infrastructure.

You will collaborate with chip architects and cross-functional teams to develop verification plans, implement SystemVerilog/UVM environments, and drive bring-up and validation to product launch.

Qualifications

• Bachelor's degree in Science, Engineering, or related field and 6+ years of ASIC design, verification, validation, integration, or related work experience.
• OR Master’s degree in Science, Engineering, or related field and 5+ years of ASIC design, verification, validation, integration, or related work experience.
• OR PhD in Science, Engineering, or related field and 4+ years of ASIC design, verification, validation, integration, or related work experience.

Responsabilités

• Leverage advanced knowledge of architecture, micro-architecture, logic design, circuits, and/or physical design to develop and verify critical high performance and secure designs.
• Anticipate, identify, and solve highly-complex problems to ensure design completeness, functionality, power, and performance.
• Collaborate with cross-functional teams to define requirements, specifications, and trade-offs (e.g., performance, power, cost, functionalities, etc.) in order to accomplish product goals.
• Evaluates all aspects of the design process from conceptualization to productization (i.e., architecture definition, feasibility, pre-silicon design and verification, and post-silicon validation) that meet customer and industry standards.
• Writes detailed technical documentation (e.g., feature descriptions, architectural descriptions, verification test plans, and implementation details, etc.) for highly complex secure subsystem designs; reviews documentation of junior engineers.
• Propose meetings and technical discussions to review Test Plans, debug issues and incorporate feedback into existing documentation and Test Plans.
• Run and Analyze Coverage reports, understand Coverage holes and re-spin Test Plans to achieve coverage metrics.

Connaissances

SystemVerilog

UVM

Synopsys VCS/Verdi

Makefile automation

Python scripting

Assertion-based verification

Functional coverage

Formation

Bachelor's degree in Science, Engineering, or related field

Master's degree in Science, Engineering, or related field

PhD in Science, Engineering, or related field

Outils

None

Description du poste

Qualcomm Technologies, Inc. is seeking a Hardware Engineer to plan, design, verify, and test complex SOC-level hardware and RF/analog systems, bringing up yield, packaging, and test infrastructure.

You will collaborate with chip architects and cross-functional teams to develop verification plans, implement SystemVerilog/UVM environments, and drive bring-up and validation to product launch.