Senior ASIC Verification Engineer: Pre-Silicon Impact

Palo Alto Networks, Inc.; Santa Clara (CA); On-site; USD 106,400 - 172,150; Full time

Job summary

Palo Alto Networks, Inc. is seeking a Design Verification Engineer for the ASIC team to ensure ASICs meet industry-leading requirements for performance and reliability.

This role involves defining verification methodologies and collaborating with engineers across teams to create comprehensive verification plans. Candidates should have a BS in Electrical Engineering, Computer Engineering, or Computer Science, with at least 3 years of experience in ASIC design verification.

The position offers a competitive salary range from $106,400 to $172,150 per year, depending on qualifications and experience.

Qualifications

• Minimum 3 years experience in ASIC design verification.
• Demonstrated success in taking multiple ASIC products from concept to mass production.
• Technical strength in defining test plans and developing functional coverage models.

Responsibilities

• Collaborate on pre-silicon verification plans across multiple methodologies.
• Plan and execute simulation test plans using coverage-driven methodologies.
• Develop flows and infrastructure for emulation.

Skills

SystemVerilog

UVM

Python

Perl

UNIX shell

ASIC design verification

Networking and cyber security

Education

BS in EE, CE, or CS

MSEE preferred

Job description

Palo Alto Networks, Inc. is seeking a Design Verification Engineer for the ASIC team to ensure ASICs meet industry-leading requirements for performance and reliability.

This role involves defining verification methodologies and collaborating with engineers across teams to create comprehensive verification plans. Candidates should have a BS in Electrical Engineering, Computer Engineering, or Computer Science, with at least 3 years of experience in ASIC design verification.

The position offers a competitive salary range from $106,400 to $172,150 per year, depending on qualifications and experience.