Senior ASIC Verification Engineer – Lead SoC Validation

Teradyne; North Reading (MA); On-site; USD 155,000 - 308,000; Full time

Benefits offered by this job

Health and well-being benefits

Retirement savings plans

Tuition assistance

Job summary

Teradyne in North Reading, MA seeks a Sr. ASIC Verification Engineer to lead verification planning and build SystemVerilog/UVM environments for complex ASIC/SoC designs.

You will work with design, architecture, firmware, software, and validation teams to ensure feature completeness and high-quality verification deliverables. Ideal candidates have 8+ years in ASIC/SoC verification, strong SystemVerilog/UVM skills, SystemC/C++, and experience with constrained-random verification and coverage

Qualifications

• Bachelor's degree in Electrical/Computer Engineering or related technical field; Master's preferred.
• 8+ years of ASIC/SoC verification experience in semiconductor product development.
• Strong experience with SystemC and C++.
• Strong Object Oriented Programming experience.
• Strong experience developing verification environments using SystemVerilog and UVM.
• Deep understanding of functional verification methodologies, constrained-random verification, and coverage closure.
• Experience with assertion-based verification and scripting (Python/Perl).
• Knowledge of industry-standard EDA simulation and debug tools.

Responsibilities

• Lead verification planning, testbench architecture, and execution for complex ASIC/SoC designs.
• Develop and maintain SystemVerilog/UVM-based verification environments, test cases, and reusable verification components.
• Collaborate with design, architecture, firmware, software, and validation teams for comprehensive coverage.
• Build and execute verification strategies using simulation, coverage-driven verification, assertions, and formal methods.
• Support debug and root-cause analysis during verification and silicon bring-up.
• Define verification requirements, milestones, and quality metrics with cross-functional teams.
• Mentor junior engineers on verification methodologies, coding practices, and debugging.
• Ensure deliverables are high quality and on schedule.

Skills

SystemVerilog

UVM

SystemC

C++

OOP

Python/Perl scripting

verification methodologies

debugging

Education

Bachelor's degree in EE/CE/CS

Master's degree preferred

Tools

SystemVerilog

UVM

EDA simulation tools

Job description

Teradyne in North Reading, MA seeks a Sr. ASIC Verification Engineer to lead verification planning and build SystemVerilog/UVM environments for complex ASIC/SoC designs.

You will work with design, architecture, firmware, software, and validation teams to ensure feature completeness and high-quality verification deliverables. Ideal candidates have 8+ years in ASIC/SoC verification, strong SystemVerilog/UVM skills, SystemC/C++, and experience with constrained-random verification and coverage