Sr. ASIC Verification Engineer (TERADYNE, North Reading, MA)

Teradyne; North Reading (MA); On-site; USD 155,000 - 308,000; Full time

Benefits offered by this job

Health and well-being benefits

Retirement savings plans

Tuition assistance

Job summary

Teradyne in North Reading, MA seeks a Sr. ASIC Verification Engineer to lead verification planning and build SystemVerilog/UVM environments for complex ASIC/SoC designs.

You will work with design, architecture, firmware, software, and validation teams to ensure feature completeness and high-quality verification deliverables. Ideal candidates have 8+ years in ASIC/SoC verification, strong SystemVerilog/UVM skills, SystemC/C++, and experience with constrained-random verification and coverage

Qualifications

• Bachelor's degree in Electrical/Computer Engineering or related technical field; Master's preferred.
• 8+ years of ASIC/SoC verification experience in semiconductor product development.
• Strong experience with SystemC and C++.
• Strong Object Oriented Programming experience.
• Strong experience developing verification environments using SystemVerilog and UVM.
• Deep understanding of functional verification methodologies, constrained-random verification, and coverage closure.
• Experience with assertion-based verification and scripting (Python/Perl).
• Knowledge of industry-standard EDA simulation and debug tools.

Responsibilities

• Lead verification planning, testbench architecture, and execution for complex ASIC/SoC designs.
• Develop and maintain SystemVerilog/UVM-based verification environments, test cases, and reusable verification components.
• Collaborate with design, architecture, firmware, software, and validation teams for comprehensive coverage.
• Build and execute verification strategies using simulation, coverage-driven verification, assertions, and formal methods.
• Support debug and root-cause analysis during verification and silicon bring-up.
• Define verification requirements, milestones, and quality metrics with cross-functional teams.
• Mentor junior engineers on verification methodologies, coding practices, and debugging.
• Ensure deliverables are high quality and on schedule.

Skills

SystemVerilog

UVM

SystemC

C++

OOP

Python/Perl scripting

verification methodologies

debugging

Education

Bachelor's degree in EE/CE/CS

Master's degree preferred

Tools

SystemVerilog

UVM

EDA simulation tools

Job description

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Date: Aug 25, 2026

Location: North Reading, MA, US

We are the global test and automation specialists, powering next-generation technologies through sophisticated solutions. Behind every electronic device you use, Teradyne's test technology ensures your device works right the first time, every time! Our portfolio of automation solutions help manufacturers to develop and deliver products quickly, efficiently and cost-effectively. Together,Teradyne companies deliver manufacturing automation across industries and applications around the world!

We attract, develop, and retain a high-performance workforce, comprised of people with diverse backgrounds and a shared drive for excellence. We strive to foster a positive and inclusive work environment that helps employees, and communities, thrive.

Opportunity Overview

As a Sr. ASIC Verification Engineer based in North Reading, MA, you will play a key role in the development and verification of complex ASIC and SoC designs that support Teradyne’s industry-leading products. You will join the ASIC Reference Model team so this requires strong technical expertise in digital design verification methodologies, collaboration across engineering disciplines, and the ability to contribute to strategic verification initiatives while driving quality and execution excellence. This senior role aligns with professionals who work on complex issues requiring conceptual thinking, implement solutions for broadly defined problems, and contribute to the success of larger cross-functional projects.

• Lead verification planning, testbench architecture, and execution for complex ASIC and SoC designs.
• Develop and maintain SystemVerilog/UVM-based verification environments, test cases, and reusable verification components.
• Collaborate closely with design, architecture, firmware, software, and validation teams to ensure comprehensive feature coverage.
• Build and execute verification strategies utilizing simulation, coverage-driven verification, assertions, and formal methodologies.
• Support debug and root-cause analysis of functional issues identified during verification and silicon bring-up activities.
• Partner with cross-functional teams to define verification requirements, milestones, and quality metrics.
• Mentor junior engineers on verification methodologies, coding practices, and debugging techniques.
• Ensure verification deliverables are completed with high quality, on schedule, and aligned with project objectives.

All About You

We seek individuals who share our passion and determination. Our commitment to customer success drives us to go the extra mile. If you're ready to join us in this mission, take a closer look at the minimum criteria for the position.

• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or related technical field; Master's degree preferred.
• 8+ years of ASIC/SoC verification experience in semiconductor product development.
• Strong experience with SystemC and C++.
• Strong Object Oriented Programming experience.
• Strong experience developing verification environments using SystemVerilog and UVM.
• Deep understanding of functional verification methodologies, constrained-random verification, and coverage closure.
• Experience with assertion-based verification and scripting using Python, Perl, or similar languages.
• Knowledge of industry-standard EDA simulation and debug tools.
• Experience verifying complex digital designs, interconnects, memory subsystems, and high-speed interfaces.
• Strong analytical and problem-solving skills with the ability to debug complex functional issues.
• Excellent collaboration and communication skills in a cross-functional engineering environment.
• Preferred experience with formal verification methodologies.
• Preferred experience supporting silicon bring-up and post-silicon validation activities.

Compensation: The base salary range for this role is $154,900-$307,600. This range is a good faith estimate, and the amount of base salary will correspond with experience and skill set. This range can also fluctuate depending on demand and location.

Incentive Plan: This job is eligible for discretionary bonus(es) based on financial performance.

Benefits: Teradyne offers a variety of robust health and well-being benefit programs, including medical, dental, vision, Flexible Spending Accounts, retirement savings plans, life and disability insurance, paid vacation & holidays, tuition assistance programs, and more.

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