Hybrid ASIC Design & Verification Engineer

Cisco; San Jose (CA); Hybrid; USD 180,000 - 260,000; Full time

Job summary

Cisco is seeking an ASIC Engineer to join our hybrid team in San Jose, CA. You will define, design, and verify ASICs and subsystems for deployment across Cisco platforms.

You will contribute to multi‑discipline engineering efforts to achieve target power, performance, and area goals, and drive block‑level design from spec to tapeout. The role emphasizes HDL coding, test benches, and design verification, with responsibilities spanning complex debugging, documentation, and collaboration across

Qualifications

• Bachelor's degree in electrical engineering with 5+ years of related experience, or Master's with 3 years, or PhD with 0 years.
• Experience in high‑performance ASIC design and integration into Cisco platforms.
• Strong HDL coding, debugging, and documentation skills.

Responsibilities

• Collaborates on the definition and design of high performance ASICs
• Oversees project code
• Owns complex code, and debugs within and outside of owned code
• Documents functional and user specs for code
• Builds out design by completing block level flow, from block spec to tapeout
• Contributes to resolution of block level issues
• Writes and executes test plans and test benches
• Leads design verification activities
• Writes and executes test plans and test benches concerning analog/mixed signal products
• Owns physical design of multiple blocks or one high complexity block
• Guides RDL block owners on RTL changes
• Drives Signal and Power integrity for the ASIC integration

Skills

ASIC design

RTL development

Verification

Power integrity

Test benches

Collaboration

Education

Bachelor's in Electrical Engineering

Tools

Verilog/SystemVerilog

Job description

Cisco is seeking an ASIC Engineer to join our hybrid team in San Jose, CA. You will define, design, and verify ASICs and subsystems for deployment across Cisco platforms.

You will contribute to multi‑discipline engineering efforts to achieve target power, performance, and area goals, and drive block‑level design from spec to tapeout. The role emphasizes HDL coding, test benches, and design verification, with responsibilities spanning complex debugging, documentation, and collaboration across