Senior ASIC Verification Engineer — High-Throughput PCIe

Broadcom Inc.; San Jose (CA); On-site; USD 122,000 - 195,000; Full time

Benefits offered by this job

Medical, dental and vision plans

401(k) with company matching

Employee Stock Purchase Program (ESPP)

Paid holidays, sick leave and vacation

Job summary

Broadcom Inc. in San Jose, CA is seeking an experienced design engineer to conceive and develop leadership silicon technology for datacenter and cloud operators.

You will work on high-speed Ethernet and PCIe devices, contribute to front-end design, and drive architecture, RTL coding and silicon validation with a global team. Ideal candidates have a BSEE with 8+ years or MSEE with 6+ years, strong scripting in Python/Perl, and solid communication skills.

Qualifications

• Requires a BSEE with 8+ years or MSEE with 6+ years of industry experience in high-speed chip architecture.
• Strong background in Ethernet controller or PCIe, RTL design and ASIC design process.
• Proficiency with Python/Perl scripting and excellent communication/documentation skills.

Responsibilities

• Lead front-end design activities for new high-performance devices.
• Define architecture, RTL coding, simulation/verification, synthesis, timing closure, and silicon validation.
• Collaborate with global design teams and provide technical leadership.

Skills

RTL design

ASIC design

Python/Perl scripting

Education

BSEE with 8+ years

MSEE with 6+ years

Job description

Broadcom Inc. in San Jose, CA is seeking an experienced design engineer to conceive and develop leadership silicon technology for datacenter and cloud operators.

You will work on high-speed Ethernet and PCIe devices, contribute to front-end design, and drive architecture, RTL coding and silicon validation with a global team. Ideal candidates have a BSEE with 8+ years or MSEE with 6+ years, strong scripting in Python/Perl, and solid communication skills.