Senior ASIC Verification Engineer — High-Speed Interconnect

Anysilicon; Irvine (CA); Ibrido; USD 140.000 - 190.000; Tempo pieno

Descrizione del lavoro

Broadcom is seeking a motivated ASIC Verification Engineer to join its HSIP Group. You will develop verification environments and testbenches using SystemVerilog UVM, understand Ethernet protocols, and contribute to block- and chip-level verification. Strong programming in C/C++ and scripting is required.

The candidate should have a Bachelor's, Master's, or PhD with related experience, with exposure to design/verification; a team-oriented, proactive attitude is essential.

Competenze

• Bachelor's degree in Engineering with 5+ years of related experience, or a Master's degree in Engineering with 3+ years of related experience, or a PhD with no experience.
• Design/Verification experience or equivalent experience.

Mansioni

• Develop a thorough understanding of IEEE Ethernet protocols.
• Understand chip architecture, microarchitecture, and design specifications.
• Develop advanced verification environments and testbench components in SystemVerilog UVM.
• Participate in block-level and chip-level verification tasks.
• Conduct infrastructure work including developing scripts and tools for efficiency and quality improvements.

Conoscenze

Verilog/SystemVerilog

C/C++ programming

Python/Perl/TCL

Team communication

Formazione

Bachelor's degree in Engineering

Master's degree in Engineering

PhD (no experience)

Strumenti

SystemVerilog UVM

Descrizione del lavoro

Broadcom is seeking a motivated ASIC Verification Engineer to join its HSIP Group. You will develop verification environments and testbenches using SystemVerilog UVM, understand Ethernet protocols, and contribute to block- and chip-level verification. Strong programming in C/C++ and scripting is required.

The candidate should have a Bachelor's, Master's, or PhD with related experience, with exposure to design/verification; a team-oriented, proactive attitude is essential.