ASIC Verification Engineer

Anysilicon; Irvine (CA); Hybrid; USD 140,000 - 190,000; Full time

Job summary

Broadcom is seeking a motivated ASIC Verification Engineer to join its HSIP Group. You will develop verification environments and testbenches using SystemVerilog UVM, understand Ethernet protocols, and contribute to block- and chip-level verification. Strong programming in C/C++ and scripting is required.

The candidate should have a Bachelor's, Master's, or PhD with related experience, with exposure to design/verification; a team-oriented, proactive attitude is essential.

Qualifications

• Bachelor's degree in Engineering with 5+ years of related experience, or a Master's degree in Engineering with 3+ years of related experience, or a PhD with no experience.
• Design/Verification experience or equivalent experience.

Responsibilities

• Develop a thorough understanding of IEEE Ethernet protocols.
• Understand chip architecture, microarchitecture, and design specifications.
• Develop advanced verification environments and testbench components in SystemVerilog UVM.
• Participate in block-level and chip-level verification tasks.
• Conduct infrastructure work including developing scripts and tools for efficiency and quality improvements.

Skills

Verilog/SystemVerilog

C/C++ programming

Python/Perl/TCL

Team communication

Education

Bachelor's degree in Engineering

Master's degree in Engineering

PhD (no experience)

Tools

SystemVerilog UVM

Job description

Broadcom is seeking a motivated ASIC Verification Engineer to join its High Speed Interconnect Product (HSIP) Group. This role involves working on cutting-edge semiconductor solutions for wired and wireless communications, specifically focusing on high-performance physical layer transceivers (PHYs) for AI data centers and enterprise networks. The ideal candidate will have a strong educational background and relevant experience in ASIC design and verification, contributing to the full product development cycle.

Responsibilities

• Develop a thorough understanding of IEEE Ethernet protocols.
• Understand chip architecture, microarchitecture, and design specifications.
• Develop advanced verification environments and testbench components in SystemVerilog UVM.
• Participate in block-level and chip-level verification tasks.
• Conduct infrastructure work including developing scripts and tools for efficiency and quality improvements.

Qualifications

• Bachelor's degree in Engineering with 5+ years of related experience, or a Master's degree in Engineering with 3+ years of related experience, or a PhD with no experience.
• Design/Verification experience or equivalent experience.

Skills

• Proficiency in HDL languages such as Verilog, SystemVerilog, or VHDL.
• Proficiency in C/C++ programming and hands-on exposure to Object Oriented Programming.
• Proficiency in scripting languages such as Python, PERL, or TCL.
• Self-motivated with strong communication skills, quick learning ability, and a good team player attitude.