Senior ASIC Verification Engineer: SystemVerilog & UVM

K2 Space Corporation; Seattle (WA); On-site; USD 190,000 - 285,000; Full time

Benefits offered by this job

Comprehensive benefits package

Paid time off

Medical/dental/vision coverage

Job summary

K2 Space Corporation is seeking a Principal ASIC Design Verification Engineer to verify functionality and performance of custom silicon designs. The role includes developing verification plans and ensuring high-quality testing techniques.

Candidates should have a strong engineering background with extensive experience in ASIC/SoC verification and a solid understanding of SystemVerilog and RTL design. The position is based in Seattle, WA and offers competitive compensation and benefits.

Qualifications

• 10+ years of experience in ASIC/SoC verification.
• Experience with test planning and UVM‑based testbench development.
• Involvement in post‑silicon validation planning and execution.

Responsibilities

• Develop and execute verification plans for blocks and full chips.
• Build SystemVerilog/UVM test benches.
• Collaborate with RTL designers to resolve issues.

Skills

SystemVerilog

Digital logic

RTL design

DFT

Hardware design and verification flows

Python

C / C++

Education

B.S. or M.S. in Electrical Engineering, Computer Engineering, or related field

Tools

VCS

Xcelium

Questa

Verdi

SimVision

Git

Job description

K2 Space Corporation is seeking a Principal ASIC Design Verification Engineer to verify functionality and performance of custom silicon designs. The role includes developing verification plans and ensuring high-quality testing techniques.

Candidates should have a strong engineering background with extensive experience in ASIC/SoC verification and a solid understanding of SystemVerilog and RTL design. The position is based in Seattle, WA and offers competitive compensation and benefits.