Senior ASIC Verification Architect

K2 Space Corporation; Los Angeles (CA); On-site; USD 190,000 - 285,000; Full time

Job summary

K2 Space Corporation is seeking a Principal ASIC Design Verification Engineer to verify the functionality, performance, and robustness of our custom silicon. You will define verification approaches, develop methodologies, and work with architecture, RTL, DFT, firmware, and validation teams in a hands-on, high-ownership role.

This role requires leading verification plans, building UVM test benches, writing SVA, and driving thorough coverage and sign-off.

Qualifications

• Experience with SystemVerilog, RTL design, DFT, and verification flows.
• Proficiency in UVM-based testbenches and coverage concepts.
• Strong scripting skills and test planning capability.

Responsibilities

• Develop and execute verification plans for block-, subsystem-, and full-chip environments.
• Build SystemVerilog/UVM test benches with agents, monitors, scoreboards, and coverage models.
• Write SystemVerilog Assertions and integrate formal verification where appropriate.
• Drive constrained-random and directed testing to validate functionality and corner cases.
• Run simulations, triage failures, and perform root-cause analysis with RTL teams.
• Maintain functional, code, and assertion coverage; ensure coverage closure for sign-off.
• Manage regression testing, simulation farms, and CI pipelines for throughput.
• Participate in design reviews and influence DFV best practices.
• Collaborate with architecture, RTL, DFT, firmware, and physical design teams.
• Support silicon bring-up and post-silicon validation via test reuse and diagnostics.

Skills

SystemVerilog

UVM

Test planning

Regression testing

C/C++

Git

CI/CD

Embedded firmware

DFT

AMBA interfaces

SVA

Post-silicon validation

Education

B.S./M.S. in Electrical/Computer Engineering

Tools

VCS

Xcelium

Questa

Verdi

SimVision

Python

Perl

TCL

Git

Job description

K2 Space Corporation is seeking a Principal ASIC Design Verification Engineer to verify the functionality, performance, and robustness of our custom silicon. You will define verification approaches, develop methodologies, and work with architecture, RTL, DFT, firmware, and validation teams in a hands-on, high-ownership role.

This role requires leading verification plans, building UVM test benches, writing SVA, and driving thorough coverage and sign-off.