Senior ASIC Verification Engineer (SoC) – Testbench Lead

Airbus Ventures; Aliso Viejo (CA); On-site; USD 165,000 - 199,000; Full time

Benefits offered by this job

Stock options

Health insurance

Dental plan

Vision plan

Retirement plan

Job summary

CesiumAstro is seeking a Principal ASIC Functional Verification Engineer to join the Design Verification team. You will design and implement verification test benches for system, chip and block level verification using SystemVerilog, UVM, OVM or VMM and develop functional coverage plans.

Requirements include a BS in CS/EE or related field with 10+ years of experience (or 8+ years with a Masters), strong knowledge of SystemVerilog and verification methodologies, and excellent communication

Qualifications

• Minimum of 10 years of relevant experience with a BS in CS, EE, CE or related field, or 8+ years with a Masters.
• Proficiency in SystemVerilog and verification methodologies.
• Experience with UVM, OVM or VMM and with SVA/PSL/OVL assertions.

Responsibilities

• Design and implement verification test bench infrastructure and test cases for system, chip and block level verification using SystemVerilog class libraries (UVM/OVM/VMM).
• Implement pseudo-random and functional coverage verification methodologies.
• Develop functional test and verification plans.
• Collaborate with the VLSI Design team to plan and implement verification strategies.

Skills

SystemVerilog

UVM/OVM/VMM

Functional coverage

Test bench design

Education

BS in CS/EE/CE

Job description

CesiumAstro is seeking a Principal ASIC Functional Verification Engineer to join the Design Verification team. You will design and implement verification test benches for system, chip and block level verification using SystemVerilog, UVM, OVM or VMM and develop functional coverage plans.

Requirements include a BS in CS/EE or related field with 10+ years of experience (or 8+ years with a Masters), strong knowledge of SystemVerilog and verification methodologies, and excellent communication