Senior ASIC Verification Architect for AI Accelerators

European Tech Recruit; San Francisco (CA); On-site; USD 130,000 - 180,000; Full time

Job summary

European Tech Recruit is partnering with a fast-growing AI technology organisation to hire a Senior ASIC Verification Engineer. You will lead verification across multi-million-gate ASICs integrating accelerators and IP, defining plans from architecture to tape-out.

Responsibilities include building scalable testbenches, verifying ARM/RISC-V CPUs, and driving sign-off criteria. Strong SystemVerilog/UVM, constrained random, and coverage-driven methods required.

Qualifications

• 4–8 years' ASIC verification experience across full lifecycle.
• Expert SystemVerilog, UVM, constrained-randomisation and functional coverage.
• Experience with C/C++ or SystemC.
• Deep understanding of object-oriented programming, constrained-random stimulus and coverage-driven verification methodologies.
• Verification experience with high-speed interfaces such as PCIe, Ethernet, DDR/HBM and SerDes.

Responsibilities

• Lead ASIC verification activities, ensuring pre-silicon correctness across complex multi-million-gate designs.
• Drive verification planning from architecture through tape-out.
• Develop block-level, subsystem and full-chip verification environments and tests.
• Lead SoC and subsystem verification of embedded CPUs, including ARM and RISC-V architectures, and interconnect subsystems.
• Develop C and assembly-based diagnostic validation tests.
• Establish reusable verification methodologies and frameworks, scaling testbenches across subsystem and full-chip environments.
• Work with design/architecture teams to verify functional and performance requirements under all operating conditions.
• Triage and debug functional and performance issues in the design under test.
• Define verification sign-off criteria and quality metrics.
• Manage bug tracking, coverage convergence and regression failures to closure.
• Mentor verification engineers in test planning and verification activities.
• Perform diagnostic and post-silicon validation testing in the lab.

Skills

SystemVerilog

UVM

Constrained random verification

Functional coverage

C/C++

SystemC

PCIe

Ethernet

DDR/HBM

SerDes

Object-oriented programming

Scripting (Python/Perl/Tcl/Shell)

Job description

European Tech Recruit is partnering with a fast-growing AI technology organisation to hire a Senior ASIC Verification Engineer. You will lead verification across multi-million-gate ASICs integrating accelerators and IP, defining plans from architecture to tape-out.

Responsibilities include building scalable testbenches, verifying ARM/RISC-V CPUs, and driving sign-off criteria. Strong SystemVerilog/UVM, constrained random, and coverage-driven methods required.