ASIC Verification Engineer

European Tech Recruit; San Francisco (CA); On-site; USD 130,000 - 180,000; Full time

Job summary

European Tech Recruit is partnering with a fast-growing AI technology organisation to hire a Senior ASIC Verification Engineer. You will lead verification across multi-million-gate ASICs integrating accelerators and IP, defining plans from architecture to tape-out.

Responsibilities include building scalable testbenches, verifying ARM/RISC-V CPUs, and driving sign-off criteria. Strong SystemVerilog/UVM, constrained random, and coverage-driven methods required.

Qualifications

• 4–8 years' ASIC verification experience across full lifecycle.
• Expert SystemVerilog, UVM, constrained-randomisation and functional coverage.
• Experience with C/C++ or SystemC.
• Deep understanding of object-oriented programming, constrained-random stimulus and coverage-driven verification methodologies.
• Verification experience with high-speed interfaces such as PCIe, Ethernet, DDR/HBM and SerDes.

Responsibilities

• Lead ASIC verification activities, ensuring pre-silicon correctness across complex multi-million-gate designs.
• Drive verification planning from architecture through tape-out.
• Develop block-level, subsystem and full-chip verification environments and tests.
• Lead SoC and subsystem verification of embedded CPUs, including ARM and RISC-V architectures, and interconnect subsystems.
• Develop C and assembly-based diagnostic validation tests.
• Establish reusable verification methodologies and frameworks, scaling testbenches across subsystem and full-chip environments.
• Work with design/architecture teams to verify functional and performance requirements under all operating conditions.
• Triage and debug functional and performance issues in the design under test.
• Define verification sign-off criteria and quality metrics.
• Manage bug tracking, coverage convergence and regression failures to closure.
• Mentor verification engineers in test planning and verification activities.
• Perform diagnostic and post-silicon validation testing in the lab.

Skills

SystemVerilog

UVM

Constrained random verification

Functional coverage

C/C++

SystemC

PCIe

Ethernet

DDR/HBM

SerDes

Object-oriented programming

Scripting (Python/Perl/Tcl/Shell)

Job description

Senior ASIC Verification Engineer – SystemVerilog / UVM / SoC Verification / AI Accelerators

We are currently partnered with a well-funded, fast-growing AI technology organisation developing high-performance, low-power generative AI inference systems. The company combines custom silicon, hardware and software to accelerate multimodal AI inference for hyperscale and neocloud data centre customers. This opportunity sits within the ASIC team, leading verification activities across next-generation processors and complex multi-million-gate ASICs integrating computational accelerators and third-party SoC IP.

Key responsibilities

• Lead ASIC verification activities, ensuring pre-silicon correctness and quality across complex multi-million-gate designs.
• Drive verification planning from architecture through to tape-out.
• Develop block-level, subsystem and full-chip verification environments and tests in line with defined test plans.
• Lead SoC and subsystem verification of embedded CPUs, including ARM and RISC-V architectures, and interconnect subsystems.
• Develop C and assembly-based diagnostic validation tests.
• Establish reusable verification methodologies and frameworks, scaling testbenches across subsystem and full-chip environments.
• Work closely with design and architecture teams to understand functional and performance requirements and verify the design under all specified operating conditions.
• Triage and debug functional and performance issues within the design under test.
• Define verification sign-off criteria and quality metrics.
• Manage bug tracking, coverage convergence and regression failures through to verification closure.
• Mentor and technically guide verification engineers throughout test planning and verification activities.
• Perform diagnostic and post-silicon validation testing in the laboratory.

Key requirements

• 4–8 years' ASIC verification experience, including taking multiple chips through the complete verification and post-silicon validation lifecycle.
• Expert-level knowledge of SystemVerilog, UVM, constrained-randomisation and functional coverage.
• Experience with C/C++ or SystemC.
• Deep understanding of object-oriented programming principles, constrained-random stimulus and coverage-driven verification methodologies.
• Verification experience with high-speed interfaces such as PCIe, Ethernet, DDR/HBM and SerDes.

Keywords

Senior ASIC Verification Engineer / ASIC Verification / Digital Verification / SystemVerilog / UVM / Constrained Random Verification / Functional Coverage / Coverage-Driven Verification / Object-Oriented Programming / OOP / Testbench Development / Verification Planning / Verification Methodology / Verification Frameworks / Block-Level Verification / Subsystem Verification / SoC Verification / Full-Chip Verification / Multi-Million-Gate ASIC / AI ASIC / AI Accelerators / Generative AI / AI Inference / ARM / RISC-V / CPU Verification / Interconnect Verification / C / C++ / SystemC / Assembly Diagnostics / PCIe / Ethernet / DDR / HBM / SerDes / Regression Testing / Coverage Closure / Bug Tracking / Verification Sign-Off / Post-Silicon Validation / Silicon Debug / Python / Perl / Tcl / Shell Scripting / Tape-Out

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