Lead ASIC Verification Architect & Testbench Leader

Chelsea Search Group; Minneapolis (MN); On-site; USD 150,000 - 190,000; Full time

Job summary

Chelsea Search Group is seeking a Lead ASIC Design Verification Engineer to establish and lead our verification team. You will architect UVM testbenches for current programs and define verification methodology, infrastructure, and hiring plans to scale the function.

You will personally implement testbenches, drive coverage-driven sign-off, and manage tapeout risk while coordinating with customers and government stakeholders on verification approaches and evidence.

Qualifications

• B.S. in Electrical Engineering, Computer Engineering, or Computer Science required.
• 8+ years of ASIC/SoC verification experience with ownership of at least one production tapeout.
• Expert-level SystemVerilog and UVM; architected UVM environments from scratch.
• Strong command of constrained-random verification, functional coverage, coverage-driven closure, and SVA.
• Experience with commercial simulation and coverage tools (VCS/Verdi, Xcelium, Questa) and regression management at scale.
• Working knowledge of digital design and RTL; able to read, reason about, and discuss intent vs. implementation.
• Scripting proficiency (Python, Perl, TCL, shell) and Git/Linus workflows.
• Demonstrated technical leadership: mentoring, leading a verification effort, or owning schedule/sign-off.
• Clear written and verbal communication; able to present status/evidence to non-verification stakeholders.
• U.S. Citizenship required for ITAR/DFARS programs and ability to obtain security clearance.

Responsibilities

• Define and own the ASIC verification methodology, standards, and sign-off criteria across programs.
• Architect UVM-based verification environments for digital SoCs and subsystems.
• Establish reusable verification infrastructure and coverage models for reuse across programs.
• Own verification planning, testplan development, coverage closure, regression architecture, and sign-off metrics.
• Serve as the verification voice in design reviews and interface with customers and stakeholders.
• Onboard, mentor, and develop verification engineers; participate in recruiting and hiring.
• Define team structure, roles, and processes; enforce code review and documentation best practices.
• Write SystemVerilog/UVM testbench code; 50–70% hands-on execution; manage regression infrastructure.

Skills

SystemVerilog

UVM

Constrained-random

Functional coverage

SVA

Python

Perl

TCL

Git workflows

Leadership

Communication

Education

B.S. in EE/CE/CS

Tools

Synopsys VCS/Verdi

Cadence Xcelium

Siemens Questa

Job description

Chelsea Search Group is seeking a Lead ASIC Design Verification Engineer to establish and lead our verification team. You will architect UVM testbenches for current programs and define verification methodology, infrastructure, and hiring plans to scale the function.

You will personally implement testbenches, drive coverage-driven sign-off, and manage tapeout risk while coordinating with customers and government stakeholders on verification approaches and evidence.