Senior ASIC Timing & Implementation Engineer

Meta; Sunnyvale (CA); On-site; USD 146,000 - 209,000; Full time

Job summary

Meta's Silicon Engineering team is building custom silicon solutions that power the infrastructure behind Meta's AI and data center workloads at scale. As an ASIC Engineer focused on Implementation, you will drive the physical realization of complex custom chips from RTL through tapeout, working across synthesis, place-and-route, timing closure, and signoff.

You will collaborate with architecture, design, and verification teams to deliver high-performance, power-efficient silicon that meets

Qualifications

• Bachelor's degree in Computer Science, Computer Engineering, relevant technical field, or equivalent practical experience.
• Bachelor's degree in Computer Science, Computer Engineering, relevant technical field, or equivalent practical experience.

Responsibilities

• Develop Timing Constraints for RTL-Synthesis and PrimeTime-STA for blocks and top-level including SOC.
• Develop SOC Timing Full chip Flat & Hierarchical Constraints for Functional & DFT Modes.
• Perform STA for full chip and Physical partition blocks using PrimeTime.
• Run Logic/Physical Synthesis using advanced optimization techniques and generate optimized Gate Level Netlist for Timing, Area, Power.
• Develop automation scripts and methodology for FE-tools including Synthesis, STA.
• Work closely with Design Engineers, DV Engineers, Emulation Engineers in supporting handoff tasks.
• Interact with Physical Design Engineers and provide timing/congestion feedback.

Skills

Timing constraints

PrimeTime-STA

Full-chip timing

Synthesis & P&R

Automation scripts

Cross-functional collaboration

Timing feedback

Education

Bachelor's degree in CS/CE or related field

Bachelor's degree in CS/CE or related field

Tools

PrimeTime

DFT tools

Job description

Meta's Silicon Engineering team is building custom silicon solutions that power the infrastructure behind Meta's AI and data center workloads at scale. As an ASIC Engineer focused on Implementation, you will drive the physical realization of complex custom chips from RTL through tapeout, working across synthesis, place-and-route, timing closure, and signoff.

You will collaborate with architecture, design, and verification teams to deliver high-performance, power-efficient silicon that meets