Senior ASIC Test & Reliability Engineer

Cisco; San Jose (CA); On-site; USD 168,000 - 245,000; Full time

Benefits offered by this job

401(k) matching

Medical, dental, and vision insurance

Paid parental leave

Disability coverage

Life insurance

Job summary

Cisco SiOps is seeking an experienced IC test engineer to lead qualification, reliability, and RMA testing for Silicon One ASICs. You will collaborate with Product Test Engineering, DFT, and Design teams to shape test strategies and hardware needs, and you will perform root-cause analysis on silicon failures.

You will develop coverage improvements, correlate ATE behavior with system failures, and help transition validated solutions to volume manufacturing, driving overall silicon quality and

Qualifications

• Bachelor’s degree or higher in Electrical or Computer Engineering or equivalent.
• 8+ years in IC test engineering, SoC/VLSI test bring-up, characterization, and production testing.
• Experience with Advantest 93000 Smartscale and Exascale for test program development, silicon debug, and characterization.
• Hands-on debugging of silicon failures down to flop or cell level.
• Proficiency in C, C++, Java, Python and 93k test methods.

Responsibilities

• Drive qualification, reliability, and RMA testing activities for Silicon One ASIC products using ATE platforms and silicon debug methodologies.
• Define ATE test strategies, qualification hardware requirements, and data analytics workflows.
• Perform silicon failure analysis and debug system-level failures to identify root causes.
• Develop and enhance test coverage by defining new patterns and parametric conditions.
• Analyze qualification data to identify trends and improve test effectiveness.

Skills

C

C++

Java

Python

SoC testing

silicon debug

Advantest 93000

Exascale

Education

Bachelor’s degree or higher in Electrical Engineering or Computer Engineering

Tools

Advantest 93000 Smartscale

Exascale

Job description

Cisco SiOps is seeking an experienced IC test engineer to lead qualification, reliability, and RMA testing for Silicon One ASICs. You will collaborate with Product Test Engineering, DFT, and Design teams to shape test strategies and hardware needs, and you will perform root-cause analysis on silicon failures.

You will develop coverage improvements, correlate ATE behavior with system failures, and help transition validated solutions to volume manufacturing, driving overall silicon quality and