Senior ASIC Implementation Lead: DSP & PPA Optimization

Arycs Technologies; Los Gatos (CA); On-site; USD 150,000 - 230,000; Full time

Job summary

Arycs Technologies in Los Gatos, CA, seeks a Staff ASIC Implementation Engineer to lead RTL-to-synthesis, timing analysis, and tapeout readiness for DSP ASIC programs. You will coordinate with RTL/verification and external backend teams to drive PPA optimization and design closure.

The role emphasizes hands-on technical leadership, development of automation scripts, and collaboration across cross-functional teams to ensure first-pass silicon success.

Qualifications

• Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or related field.
• 10+ years of experience in ASIC digital implementation.
• Strong experience with RTL-to-synthesis flows (Design Compiler, Fusion Compiler).
• Deep understanding of static timing analysis and timing closure (PrimeTime).
• Experience with low-power implementation methodologies including UPF.
• Experience performing RTL power analysis and optimization (RTL Architect, PrimePower, PrimePower RTL).
• Experience debugging post-layout timing issues and guiding resolution with backend implementation teams.
• Experience supporting or driving designs through successful ASIC tapeout.
• Strong scripting skills (Tcl, Python) for automation and analysis of implementation flows.

Responsibilities

• Digital Implementation: lint, CDC, RDC checks; develop automation to run analyses; RTL-to-synthesis flows; timing constraints; power/area optimization.
• Backend Coordination: interface with external backend teams; guide timing, congestion, implementation closure; review metrics.
• Timing Closure and Tapeout Readiness: support timing closure; ensure designs meet timing, power, integration requirements; tapeout preparation.
• Cross-Team Collaboration: coordinate with RTL/verification and backend vendors; manage schedules and task visibility; risk communication.
• Implementation Methodology and Tool Flow: develop and maintain flows, automation, and scripts; collaborate with EDA vendors to improve efficiency.

Skills

RTL-to-synthesis

Timing closure

Automation scripting

Backend coordination

Education

Bachelor's or Master's in Electrical/Computer Engineering

Tools

Design Compiler

Fusion Compiler

PrimeTime

UPF

RTL Architect/PrimePower

Job description

Arycs Technologies in Los Gatos, CA, seeks a Staff ASIC Implementation Engineer to lead RTL-to-synthesis, timing analysis, and tapeout readiness for DSP ASIC programs. You will coordinate with RTL/verification and external backend teams to drive PPA optimization and design closure.

The role emphasizes hands-on technical leadership, development of automation scripts, and collaboration across cross-functional teams to ensure first-pass silicon success.