Hybrid ASIC Timing & SDC Engineer

CAONE; San Jose (CA); Hybrid; USD 150,000 - 190,000; Full time

Job summary

CAONE in San Jose, CA is seeking an experienced ASIC Design Hardware Engineer focused on SDC/STA. You will develop timing constraints, work with front-end/back-end teams, and validate constraints with industry tools to enable physical design closure.

Candidates should have a degree in Electrical or Computer Engineering and 6+ years of ASIC experience (or a Master’s with 3+ years). Proficiency in Verilog/SystemVerilog, TCL, and Primetime is required, with strong scripting and problem-solving

Qualifications

• Bachelor’s or Master’s in Electrical or Computer Engineering with relevant ASIC experience.
• Experience with synthesis tools and STA tools; Verilog/SystemVerilog proficiency.
• Strong scripting skills in Shell, Perl, and TCL; experience with timing constraints.

Responsibilities

• Develop block-level and full-chip SDCs; collaborate with PD and DFT teams to close timing.
• Develop timing constraints; validate with verification tools before release to physical design.
• Option to perform RTL integration or top-level IP integration.
• Promote block-level SDCs to full-chip and push full-chip SDCs down to blocks.
• Ensure correctness and quality of SDCs early in the design cycle.
• Review block-level SDCs and clocking diagrams with RTL owners.
• Contribute to full-chip clocking design diagrams and related documentation.

Skills

SDC/STA

Verilog/SystemVerilog

TCL scripting

Shell scripting

Primetime

Synopsys DC/DCG/FC

Clocking concepts

Timing closure

Education

Electrical Engineering

Computer Engineering

Tools

Primetime

Synopsys

Job description

CAONE in San Jose, CA is seeking an experienced ASIC Design Hardware Engineer focused on SDC/STA. You will develop timing constraints, work with front-end/back-end teams, and validate constraints with industry tools to enable physical design closure.

Candidates should have a degree in Electrical or Computer Engineering and 6+ years of ASIC experience (or a Master’s with 3+ years). Proficiency in Verilog/SystemVerilog, TCL, and Primetime is required, with strong scripting and problem-solving