Senior ASIC Power Engineer — EDA & Power Optimization

RiseMe; Sunnyvale (TX); On-site; USD 114,000 - 172,000; Full time

Benefits offered by this job

Bonus

Equity

Benefits

Job summary

Meta is seeking an experienced ASIC Engineer specializing in power analysis to develop and maintain power analysis flows, define power methodologies, and collaborate across RTL, PD, and verification teams. You will drive power closure across multi-project tapeouts, evaluate EDA tools, and implement UPF/CPF specifications to ensure consistent power intent across RTL-to-GDSII flows.

The role requires a strong background in Python/Tcl/Shell scripting, and a track record of improving power signoff

Qualifications

• Bachelor's degree in CS/CE or equivalent; degree completed before joining Meta.
• 6+ years of ASIC design/physical design with a focus on power analysis/optimization.
• Experience with EDA power analysis flows using tools like PrimePower or Voltus.
• Experience applying UPF/CPF across RTL-to-GDSII flows.
• Scripting experience in Python, Tcl, or shell to automate flows.
• Experience collaborating across RTL, PD, and verification to drive power closure.

Responsibilities

• Develop and maintain power analysis flows including dynamic and static power estimation, vectorless analysis, and power intent verification using industry-standard EDA tools
• Define and implement power methodology guidelines for RTL, synthesis, and physical design stages of the ASIC development flow
• Collaborate with RTL design, physical design, and verification teams to identify and resolve power hotspots across custom ASIC designs
• Build and optimize EDA infrastructure scripts and automation frameworks to improve power signoff accuracy and turnaround time
• Evaluate and integrate commercial and internally developed EDA tools into the power analysis flow, providing technical assessments
• Develop power intent specifications using UPF or CPF and ensure consistent application across design and implementation stages
• Establish power budgets and track power metrics across design milestones, communicating results and risks
• Drive continuous improvement of power closure methodologies by analyzing results across multiple tape-outs
• Provide technical guidance to other engineers on power analysis best practices, flow usage, and debug techniques
• Partner with EDA tool vendors to evaluate new capabilities and influence tool roadmaps to meet Meta silicon design requirements

Skills

Power analysis

Python scripting

Tcl scripting

Shell scripting

Cross-disciplinary collaboration

Education

Bachelor's degree in CS/CE or equivalent

Tools

Synopsys PrimePower

Cadence Voltus

UPF/CPF

Job description

Meta is seeking an experienced ASIC Engineer specializing in power analysis to develop and maintain power analysis flows, define power methodologies, and collaborate across RTL, PD, and verification teams. You will drive power closure across multi-project tapeouts, evaluate EDA tools, and implement UPF/CPF specifications to ensure consistent power intent across RTL-to-GDSII flows.

The role requires a strong background in Python/Tcl/Shell scripting, and a track record of improving power signoff