Staff ASIC Power Engineer, ML Accelerators

Anysilicon; Sunnyvale, Northern (CA, KY); Hybrid; USD 185,000 - 250,000; Full time

Job summary

Google in Sunnyvale, CA is seeking a Staff ASIC Power Engineer for ML Accelerators to drive power efficiency in advanced AI hardware. You will lead power modeling, architecture-level optimizations, and collaborate with software and system teams to meet dynamic power targets.

You should have a strong background in power design and SoC architecture, with leadership experience and a proven track record delivering complex projects end-to-end in a fast-paced environment.

Qualifications

• Bachelor's degree in Electrical/Computer Engineering or related field; equivalent experience accepted.
• 10 years of design or architecture experience in power-related domains.
• Experience with power design, modeling, architecture or reduction methodologies.

Responsibilities

• Contribute to design power modeling and converge to power targets.
• Investigate, specify and deploy architectural and microarchitectural power optimization techniques.
• Define best practices for low-power RTL designs.
• Collaborate with cross-functional teams to create power management architectures meeting dynamic targets.
• Lead power team to deliver complex projects end-to-end.

Skills

Power modeling

Technical leadership

Problem solving

DVFS & thermal management

Collaborative skills

Education

Bachelor's degree in EE/CE/CS

Master's or PhD in EE/CE/CS (preferred)

Tools

Power design tools

RTL power analysis

SoC design tools

Power modeling software

Job description

Staff ASIC Power Engineer, ML Accelerators

Join Google's AI and Infrastructure team as a key contributor to the future of AI/ML hardware acceleration. This role focuses on driving power efficiency for Tensor Processing Units (TPUs), essential for powering Google's most demanding AI applications. You will leverage your expertise in power design and optimization to develop innovative solutions that enhance the performance and efficiency of custom silicon technologies.

Responsibilities:

• Contribute to design power modeling and drive convergence to power targets.
• Investigate, spec, and deploy architectural and microarchitectural power optimization techniques.
• Define best practices and methodologies to achieve low-power RTL designs.
• Collaborate with cross-functional software and system teams to create novel power management architectures to meet dynamic power targets.
• Lead an experienced power team, owning the execution and delivery of complex technical projects end to end.

Qualifications:

• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
• 10 years of experience in design or architecture, including logic design, power architecture, performance, or SoC design.
• Experience with power design, modeling, architecture, or reduction methodologies.

Skills:

• Master's degree or PhD in Electrical Engineering, Computer Engineering, or Computer Science, with an emphasis on computer architecture (preferred).
• Experience defining and implementing chip-wide power management architectures and designs.
• Technical leadership and project ownership with a successful delivery track record.
• Understanding of modern power and thermal management techniques at silicon and system levels, including DVFS and Turboing.
• Ability to solve open-ended power and performance problems under ambiguity.