Physical Design Engineer

Lancesoft; San Diego (CA); On-site; USD 120,000 - 160,000; Full time

Job summary

Lancesoft is seeking highly motivated Physical Design Engineers across multiple career levels to join our ASIC implementation team in San Diego, CA. You will contribute to the development and execution of advanced physical design methodologies for complex, high‑performance SoCs and IP blocks.

You will collaborate with architecture, RTL, DFT, verification, CAD, and product engineering teams to implement designs from synthesis through final tapeout.

Qualifications

• Bachelor's degree or higher in a relevant field with ASIC experience.
• Experience in digital ASIC physical implementation methodologies.
• Understanding of power, performance, area, timing tradeoffs.
• Experience with Linux/Unix environments.
• Scripting in Python, Tcl, Perl, Shell, or similar languages.
• Experience with complete Physical Design Flow from synthesis to tapeout.

Responsibilities

• Lead physical design execution for large subsystems or critical SoC partitions.
• Define implementation strategies to achieve aggressive power, performance, area, and schedule objectives.
• Drive cross-functional alignment among Design, DFT, CAD, Verification, and Product Engineering teams.
• Develop scalable methodologies, flow improvements, and automation solutions across projects.
• Act as a technical SME in advanced physical implementation and design closure.
• Experience with complete Physical Design Flow from synthesis through tapeout.
• Knowledge of MMMC implementation methodologies and advanced-node design closure.
• Experience with DFT-aware implementation and functional timing constraints.
• Experience with RC extraction and signal integrity analysis.

Skills

Physical design

Timing closure

Low-power design techniques

Automation

Collaboration & leadership

Linux/Unix

Python scripting

Tcl scripting

Education

Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field

Master's degree in Science, Engineering, or related field

PhD in Science, Engineering, or related field

Tools

Cadence Innovus

Synopsys Fusion Compiler

Synopsys PrimeTime

RC extraction tools

Job description

We also have position in Santa Clara, CA and Austin, TX

JOB DESCRIPTION

We are seeking highly motivated Physical Design Engineers across multiple career levels to join our growing ASIC implementation team. In this role, you will contribute to the development and execution of advanced physical design methodologies for complex, high performance, low-power SoCs and IP blocks.

You will work closely with architecture, RTL, DFT, verification, CAD, and product engineering teams to implement and deliver industry leading designs from synthesis through final tapeout.

The ideal candidate possesses strong technical expertise in physical implementation, timing closure, low-power design techniques, automation, and design optimization.

Depending on experience and demonstrated technical leadership, candidates may be considered for Engineer, Senior Engineer, Staff Engineer, or Principal Engineer opportunities.

Physical Design responsibilities include floorplanning, power planning, place and route, clock tree synthesis, timing closure, signal integrity analysis, physical verification, ECO implementation, and design signoff activities.

The role supports client's advanced SoC and core design programs across GPU, Multimedia, AI, Compute, Connectivity, Modem, DDR, Audio, and other next-generation technologies.

Minimum Qualifications

Bachelor's degree in Science, Engineering, or related field and 4+ years of ASIC design, verification, validation, integration, or related work experience.

OR Master's degree in Science, Engineering, or related field and 3+ years of ASIC design, verification, validation, integration, or related work experience.

OR PhD in Science, Engineering, or related field and 2+ years of ASIC design, verification, validation, integration, or related work experience.

Experience:

3+ years industry experience

Lead physical design execution for large subsystems or critical SoC partitions.

Define implementation strategies to achieve aggressive power, performance, area, and schedule objectives.

Drive cross-functional technical alignment among Design, DFT, CAD, Verification, and Product Engineering teams.

Develop scalable methodologies, flow improvements, and automation solutions adopted across projects.

Act as a technical subject matter expert in advanced physical implementation and design closure.

Minimum Qualifications

Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related technical field and relevant experience in ASIC design, implementation, verification, validation, integration, or related engineering disciplines.

Experience with digital ASIC physical implementation methodologies.

Understanding of power, performance, area, timing, and physical design tradeoffs.

Experience working in Linux/Unix environments.

Programming or scripting experience utilizing Python, Tcl, Perl, Shell, or similar languages.

Strong analytical, problem-solving, and debugging skills.

Experience with complete Physical Design Flow from synthesis through tapeout.

Physical design expertise including floorplanning, power planning, placement, CTS, routing, timing optimization, and closure

Experience using Cadence Innovus and/or Synopsys Fusion Compiler.

Static Timing Analysis and timing closure experience using Synopsys PrimeTime.

Knowledge of MMMC implementation methodologies and advanced-node design closure.

Experience with DFT-aware implementation and functional timing constraints.

Experience with RC extraction, signal integrity analysis, cross-talk analysis, ECO implementation, and formal verification.

Experience with low-power implementation techniques, UPF methodologies, and power domain analysis.

Strong communication, collaboration, and technical leadership capabilities.

Technical Expertise Areas Successful candidates may possess expertise in one or more of the following areas: