Senior ASIC & Memory Architect for High Performance SOC

Apple Inc.; Santa Clara (CA); On-site; USD 176,000 - 312,000; Full time

Benefits offered by this job

Medical & dental

Stock options

Tuition reimbursement

Job summary

Apple Inc. in Santa Clara is seeking an experienced engineer to join our ASIC design team focused on memory subsystem architecture. You will drive RTL/micro-architecture, high‑performance memory designs, and DRAM controller/PHY development, including calibration and interconnect strategies.

You will collaborate with performance and validation teams, document study results, and help publish insights that influence next‑generation Apple hardware, while shaping efficient memory hierarchies for SOCs.

Qualifications

• Experience in ASIC design with memory subsystems.
• Strong background in DRAM controllers and PHY architectures.
• Ability to characterize performance and publish results.

Responsibilities

• Lead memory subsystem architecture research and development.
• Develop RTL/micro-architecture for high-performance memory systems.
• Collaborate on calibration algorithms and training mechanisms.
• Document findings and present results to teams and leadership.

Skills

Architecture research

RTL/micro-architecture

Memory systems design

Performance modeling

Documentation & publishing

Education

Bachelor's Degree +10 Years Experience

Job description

Apple Inc. in Santa Clara is seeking an experienced engineer to join our ASIC design team focused on memory subsystem architecture. You will drive RTL/micro-architecture, high‑performance memory designs, and DRAM controller/PHY development, including calibration and interconnect strategies.

You will collaborate with performance and validation teams, document study results, and help publish insights that influence next‑generation Apple hardware, while shaping efficient memory hierarchies for SOCs.