ASIC Design Engineer - Memory Systems & DRAM

Apple Inc.; Santa Clara (CA); On-site; USD 129,300 - 194,700; Full time

Job summary

Apple Inc. in Santa Clara, CA, is seeking an engineer to join a team focused on ASIC design for next‑generation memory systems. The role emphasizes architecture research, RTL/micro-architecture work, and characterizing performance of high‑speed memory subsystems.

The candidate will contribute to DRAM interfaces, calibration techniques, and SOC memory hierarchies, collaborating with performance teams to optimize power, area, and speed.

Qualifications

• Bachelor's degree and relevant experience.
• Experience in ASIC design and memory architectures.
• Characterizing performance and publishing results.

Responsibilities

• Lead architecture research and development of memory system architectures.
• Design RTL/micro-architecture components for high-performance memory subsystems.
• Work on DRAM interface calibration and training mechanisms.

Skills

ASIC design

Architecture research

RTL/micro-architecture

Memory subsystem

DFI interface

DRAM interface calibration

Performance modeling

Education

Bachelor's Degree

Tools

Simulation tools

Perf simulators

Job description

Apple Inc. in Santa Clara, CA, is seeking an engineer to join a team focused on ASIC design for next‑generation memory systems. The role emphasizes architecture research, RTL/micro-architecture work, and characterizing performance of high‑speed memory subsystems.

The candidate will contribute to DRAM interfaces, calibration techniques, and SOC memory hierarchies, collaborating with performance teams to optimize power, area, and speed.