Senior ASIC/FPGA Verification Engineer - SystemVerilog & UVM

Collins Aerospace; Cedar Rapids (IA); On-site; USD 86,800 - 165,200; Full time

Benefits offered by this job

Medical, dental, and vision insurance

Three weeks of vacation

Generous 401(k) plan

Tuition reimbursement

Life insurance and disability coverage

Job summary

Collins Aerospace in Cedar Rapids is looking for a verification engineer to design and develop verification environments using SystemVerilog and contribute to project verification teams.

The ideal candidate should have at least 5 years of relevant experience in ASIC/FPGA with strong knowledge of RTL coding and verification methodologies. We offer competitive benefits and a salary range from $86,800 to $165,200 depending on experience.

Qualifications

• Requires a degree in Science, Technology, Engineering or Mathematics and minimum 5 years of relevant experience.
• Active and transferable U.S. government issued security clearance is required prior to start date.
• U.S. citizenship is required for security clearance eligibility.

Responsibilities

• Verify environment architecture and design using SystemVerilog with OVM/UVM.
• Create written test plans, test cases, and coverage tracking.
• Develop testbenches for verification of RTL blocks.

Skills

ASIC/FPGA experience with RTL coding

SystemVerilog

VHDL

Chip-level verification methodologies

Communication skills

Education

Degree in STEM

Tools

QuestaSim

Quartus

Synplify

Vivado

Git

Job description

Collins Aerospace in Cedar Rapids is looking for a verification engineer to design and develop verification environments using SystemVerilog and contribute to project verification teams.

The ideal candidate should have at least 5 years of relevant experience in ASIC/FPGA with strong knowledge of RTL coding and verification methodologies. We offer competitive benefits and a salary range from $86,800 to $165,200 depending on experience.