Senior ASIC/FPGA Verification Engineer - Defense V&V Leader

RTX; Fort Wayne (IN); In loco; USD 87.000 - 165.000; Tempo pieno

Vantaggi offerti da questo lavoro

Health insurance

Tuition reimbursement

Student Loan Repayment

Relocation assistance

Descrizione del lavoro

RTX, a leading aerospace and defense company, seeks a Senior ASIC/FPGA Verification Engineer for its ART Microelectronics Technology team in Fort Wayne, IN. You will verify RTL designs, build SystemVerilog testbenches, and mentor junior engineers on on-site projects.

The role demands 5+ years in FPGA/ASIC verification, VHDL/Verilog proficiency, and UVM alignment, with strong collaboration across design and validation groups.

Competenze

• STEM degree and 5+ years relevant FPGA/ASIC experience.
• Active U.S. government security clearance and U.S. citizenship.
• Experience simulating RTL designs with VHDL/Verilog in FPGA/ASIC environment.
• Proven RTL verification testbenches using VHDL/SystemVerilog.
• Familiar with Unix/Linux and version control (Git/Subversion).

Mansioni

• Architecture and design of verification environments with SystemVerilog.
• Create test plans, cases, and coverage tracking.
• Develop testbenches for RTL blocks using VHDL or SystemVerilog.
• Collaborate with design engineers on ASIC/FPGA validation.
• Mentor junior engineers and potentially lead project verification teams.

Conoscenze

SystemVerilog

OVM/UVM

Testbench development

RTL verification

VHDL

Git/Subversion

Test plans & coverage

Formazione

Bachelor's degree in STEM

Strumenti

QuestaSim

Synplify

Quartus

Vivado

Descrizione del lavoro

RTX, a leading aerospace and defense company, seeks a Senior ASIC/FPGA Verification Engineer for its ART Microelectronics Technology team in Fort Wayne, IN. You will verify RTL designs, build SystemVerilog testbenches, and mentor junior engineers on on-site projects.

The role demands 5+ years in FPGA/ASIC verification, VHDL/Verilog proficiency, and UVM alignment, with strong collaboration across design and validation groups.