Senior ASIC/FPGA Architect - RTL & Tape-Out Lead

Anysilicon; Boise (ID); Hybrid; USD 180,000 - 240,000; Full time

Job summary

Anysilicon is seeking an experienced ASIC Lead Engineer to drive RTL design and oversee the full ASIC design lifecycle. The role requires hands-on technical leadership, independence, and collaboration across teams to ensure tape-out of complex silicon.

Ideal candidates bring extensive ASIC/FPGA design experience, especially in advanced nodes, and can define architecture, lead RTL development, and manage verification activities. DoD clearance and US citizenship are required.

Qualifications

• Bachelor's degree in Electrical or Computer Engineering or related field.
• DoD Secret security clearance required at time of hire.
• U.S. citizenship required.
• 10+ years of relevant experience; or 8+ years with a Master's degree.

Responsibilities

• Define ASIC/FPGA technical approach from concept to silicon.
• Lead RTL development focusing on correctness and clock domain crossings.
• Oversee synthesis, place & route, and STA for advanced nodes.
• Own verification plans and lead test and simulation activities.
• Mentor junior and mid-level engineers; drive process improvements.

Skills

RTL design

ASIC/FPGA engineering

Independent contributor

Leadership

Education

Bachelor's degree in Electrical or Computer Engineering

Master's degree (optional)

Tools

EDA tools

Job description

Anysilicon is seeking an experienced ASIC Lead Engineer to drive RTL design and oversee the full ASIC design lifecycle. The role requires hands-on technical leadership, independence, and collaboration across teams to ensure tape-out of complex silicon.

Ideal candidates bring extensive ASIC/FPGA design experience, especially in advanced nodes, and can define architecture, lead RTL development, and manage verification activities. DoD clearance and US citizenship are required.