Senior ASIC Formal Verification Lead, SoC/IP

Meta; Sunnyvale (CA); On-site; USD 178,000 - 250,000; Full time

Job summary

Meta is seeking an ASIC Formal Verification Engineer within the Infrastructure group to build IP and SoCs for data center applications. You will develop comprehensive formal test plans and sign-off for complex blocks, collaborating with architecture, design, and full-stack teams toward first-pass silicon success.

You will drive FV methodology, lead verification across IP/SoC, and mentor engineers while evaluating EDA tools and building scalable verification environments.

Qualifications

• Bachelor's degree in Computer Science, Computer Engineering, or related field (or equivalent practical experience).
• 8+ years in Design Verification, 5+ years in Formal Verification.
• Fluency with SystemVerilog and SVA; scripting in Python/Perl/Tcl.
• Experience with formal verification tools (JasperGold, VC-Formal).
• Ability to lead cross-functional FV efforts and mentor engineers.

Responsibilities

• Provide technical leadership in Formal Verification.
• Propose, implement and evangelize the FV methodology across the group.
• Collaborate with Architecture and Design to define formal specifications.
• Define scope, create formal environments, and close coverage at IP/Subsystem/SoC level.
• Build reusable/scalable FV environments and deploy tooling.
• Evaluate and recommend EDA solutions for FV.
• Provide training and mentoring on FV technology.

Skills

Formal Verification

SystemVerilog / SVA

Python / Perl / Tcl

JasperGold

VC-Formal

Block-level / SoC verification

Automation flows for formal

Interpret hardware specs for FV

Complex SoCs experience

Education

Bachelor's degree in Computer Science, Computer Engineering, or related field

Tools

JasperGold

VC-Formal

Job description

Meta is seeking an ASIC Formal Verification Engineer within the Infrastructure group to build IP and SoCs for data center applications. You will develop comprehensive formal test plans and sign-off for complex blocks, collaborating with architecture, design, and full-stack teams toward first-pass silicon success.

You will drive FV methodology, lead verification across IP/SoC, and mentor engineers while evaluating EDA tools and building scalable verification environments.