ASIC Engineer, Formal Verification

Meta; Sunnyvale, Austin (CA, TX); Presencial; USD 178.000 - 250.000; Jornada completa

Descripción de la vacante

Meta is seeking an ASIC Formal Verification Engineer within the Infrastructure group to build IP and SoCs for data center applications. You will develop comprehensive formal test plans and sign-off for complex blocks, collaborating with architecture, design, and full-stack teams toward first-pass silicon success.

You will drive FV methodology, lead verification across IP/SoC, and mentor engineers while evaluating EDA tools and building scalable verification environments.

Formación

• Bachelor's degree in Computer Science, Computer Engineering, or related field (or equivalent practical experience).
• 8+ years in Design Verification, 5+ years in Formal Verification.
• Fluency with SystemVerilog and SVA; scripting in Python/Perl/Tcl.
• Experience with formal verification tools (JasperGold, VC-Formal).
• Ability to lead cross-functional FV efforts and mentor engineers.

Responsabilidades

• Provide technical leadership in Formal Verification.
• Propose, implement and evangelize the FV methodology across the group.
• Collaborate with Architecture and Design to define formal specifications.
• Define scope, create formal environments, and close coverage at IP/Subsystem/SoC level.
• Build reusable/scalable FV environments and deploy tooling.
• Evaluate and recommend EDA solutions for FV.
• Provide training and mentoring on FV technology.

Conocimientos

Formal Verification

SystemVerilog / SVA

Python / Perl / Tcl

JasperGold

VC-Formal

Block-level / SoC verification

Automation flows for formal

Interpret hardware specs for FV

Complex SoCs experience

Educación

Bachelor's degree in Computer Science, Computer Engineering, or related field

Herramientas

JasperGold

VC-Formal

Descripción del empleo

Summary:

Meta is hiring ASIC Formal Verification Engineer within the Infrastructure organization. We are looking for individuals with experience in Formal Verification to build IP and System On Chip (SoC) for data center applications. As a Formal Verification Engineer, you will be part of a team working with experienced engineers across the industry, focused on developing innovative ASIC solutions for Meta’s data center applications. You will be developing comprehensive formal testplans and be responsible for complete formal verification sign-off of single or multiple complex blocks. The role also provides ample opportunities to partner and collaborate with full stack software, hardware, ASIC Design, Emulation and Post-Silicon teams towards creating a first-pass silicon success.

Required Skills:

ASIC Engineer, Formal Verification Responsibilities:

1. Provide technical leadership in Formal Verification
2. Propose, implement and evangelize the Formal Verification Methodology to be used across the group, both at the top level and at the block level
3. Work with Architecture and Design team to come up with formal specification and implementation
4. Define formal verification scope, create formal environment and close coverage with targeted Formal Verification Techniques at IP, Subsystem and SoC level
5. Build reusable/scalable environments for Formal Verification and deploying the tools
6. Evaluate and recommend EDA solutions for Formal Verification
7. Provide training for internal teams and mentoring engineers on Formal Verification technology related to Formal Verification Technology

Minimum Qualifications:

1. Bachelor's degree in Computer Science, Computer Engineering, relevant technical field, or equivalent practical experience
2. 8+ years of experience in Design Verification
3. 5+ years of experience in Formal Verification
4. Experience with Formal Verification applications including Datapath, sequential equivalence, Xprop, Clock Gating, connectivity etc
5. Proven understanding of Formal Verification methodologies, complexity reduction techniques and abstraction techniques
6. Proven analytical skills to craft novel solutions to tackle industry-level complex designs
7. Experience collaborating with cross-functional teams such as design, architecture, and software to deliver verification milestones
8. Fluency in hardware description languages, such as SystemVerilog and SVA
9. Proficiency in scripting languages such as Python, Perl, or Tcl
10. Experience with JasperGold or VC-Formal

Preferred Qualifications:

1. Experience with development of fully automated flows from specification to fully verified designs
2. Experience interpreting hardware specifications and extracting design behaviors and properties for formal verification
3. Experience with complex SoCs
4. Formal verification experience in clock domain crossing, IP-XACT based register verification and low power
5. Experience with simulators and waveform debugging tools
6. Experience in formal property verification of complex compute blocks such as DSP, CPU, GPU or HW accelerators

Public Compensation:

$178,000/year to $250,000/year + bonus + equity + benefits

Industry:

Internet

Equal Opportunity:

Meta is proud to be an Equal Employment Opportunity and Aff­rmative Action employer. We do not discriminate based upon race, religion, color, national origin, sex (including pregnancy, childbirth, or related medical conditions), sexual orientation, gender, gender identity, gender expression, transgender status, sexual stereotypes, age, status as a protected veteran, status as an individual with a disability, or other applicable legally protected characteristics. We also consider qualified applicants with criminal histories, consistent with applicable federal, state and local law. Meta participates in the E-Verify program in certain locations, as required by law. Please note that Meta may leverage artificial intelligence and machine learning technologies in connection with applications for employment.

Meta is committed to providing reasonable accommodations for candidates with disabilities in our recruiting process. If you need any assistance or accommodations due to a disability, please let us know at [e-mail].