Senior ASIC Formal Verification Engineer

US Health Partners, LLC; San Jose, Northern (CA, KY); Hybrid; USD 140,000 - 170,000; Full time

Benefits offered by this job

Medical/dental/vision benefits

Waiver credit $500/mo for medical waiv

Housing subsidy $2.5k/mo

Relocation support

Wellness benefits

Daily lunch and dinner

Job summary

Etched seeks a Formal Verification Engineer to advance verification across ASIC DV, interface IP, and SoC subsystems powering our ASICs. You will drive formal properties, enable proof convergence, and collaborate with architects, RTL designers, DV, emulation, software and firmware teams to prove design correctness and minimize corner-case bugs.

Expect to build reusable formal environments, employ SystemVerilog Assertions, and align verification with simulation and regression.

Qualifications

• 5+ years of design verification experience, including formal verification on complex digital designs or shipping silicon.
• Strong proficiency with SystemVerilog, SystemVerilog Assertions, and formal verification methodology.
• Experience with commercial formal tools such as Cadence JasperGold, Synopsys VC Formal, or Siemens Questa Formal.
• Strong understanding of digital design, computer architecture, datapaths, interconnects, memory systems, and standard SoC interfaces.
• Ability to model complex design behavior using assumptions, abstractions, constraints, cut-points, checkers, and reference models.
• Strong debugging skills across RTL, specifications, formal counterexamples, simulation waveforms, and verification reports.
• Experience collaborating across architecture, RTL design, UVM DV, emulation, software, firmware, and vendor teams.
• You thrive in a fast-paced startup environment and can take ownership of ambiguous, high-impact verification problems.

Responsibilities

• Define and drive formal verification strategy across the ASIC DV team for complex IP blocks, interface subsystems, and SoC integration logic.
• Develop formal verification plans covering functional correctness, connectivity, ordering, reset behavior, configuration legality, and deadlock/livelock freedom.
• Build reusable formal environments using SystemVerilog Assertions, assumptions, constraints, checkers, cut-points, abstraction models, and reference models.
• Drive proof convergence using abstractions, cut-points, assume-guarantee reasoning, cover properties, bounded-proof analysis, and coverage metrics to establish formal sign-off confidence.
• Work with architects and RTL designers to translate design intent and specifications into high-value formal properties and closure criteria.
• Partner with UVM DV, emulation, software, and firmware teams to align formal verification with simulation, coverage, regressions, and bring-up.
• Debug complex RTL, protocol, datapath, connectivity, and integration bugs using formal counterexamples, waveforms, and design analysis.
• Contribute to formal sign-off methodology, regression automation, reporting, and design-for-formal best practices.

Skills

SystemVerilog

SystemVerilog Assertions

Formal verification methodology

Debugging

Cross-team collaboration

Startup adaptability

Python scripting

Tools

Cadence JasperGold

Synopsys VC Formal

Siemens Questa Formal

Job description

Etched seeks a Formal Verification Engineer to advance verification across ASIC DV, interface IP, and SoC subsystems powering our ASICs. You will drive formal properties, enable proof convergence, and collaborate with architects, RTL designers, DV, emulation, software and firmware teams to prove design correctness and minimize corner-case bugs.

Expect to build reusable formal environments, employ SystemVerilog Assertions, and align verification with simulation and regression.