Senior ASIC Design Engineer: DSP, SerDes & Mixed-Signal

Celero Communications, Inc.; Irvine, Northern (CA, KY); Hybrid; USD 150,000 - 250,000; Full time

Job summary

Celero Communications, Inc. in Irvine, CA is seeking a highly skilled ASIC Design Engineer to drive development of high-speed digital ASICs for optical communication systems.

The role focuses on Verilog/SystemVerilog, DSP and SerDes, RTL, and collaborating across Analog, Verification, and Physical Design to deliver tapeout-ready silicon. You will engage in synthesis, timing analysis, CDC, and PPA optimization, with scripting in Python or Tcl to automate flows; 5+ years in digital ASIC design

Qualifications

• Bachelor's or higher degree in Electrical Engineering, Computer Engineering, or a related field.
• 5+ years of experience in digital ASIC design, with ownership of complex ASIC blocks or subsystems.
• Strong proficiency in Verilog and/or SystemVerilog.
• Strong understanding of digital design principles, RTL design, and ASIC development methodologies.
• Hands-on experience with ASIC design flows and industry-standard EDA tools.
• Knowledge of DSP, high-speed SerDes, analog/mixed-signal ICs, digital communications, or optical communications.

Responsibilities

• Design and implement high-performance digital circuits and ASIC blocks using Verilog and SystemVerilog.
• Develop and integrate DSP, digital communication, and high-speed SerDes functionality into complex ASIC designs.
• Collaborate with Analog, SerDes, DSP, Architecture, Verification, Physical Design, and Systems teams to develop mixed-signal ASICs.
• Participate in the design and development of high-speed data paths, signal processing blocks, control logic, and interfaces for optical communication systems.
• Perform synthesis, timing analysis, lint, formal equivalence, CDC, and related ASIC implementation and signoff activities.
• Optimize designs for performance, power, and area (PPA).
• Perform RTL simulation and debugging to ensure design functionality and performance.
• Contribute to block-level and top-level integration, verification, and silicon bring-up.
• Participate in architecture and design reviews and provide technical guidance to other engineers.
• Collaborate with cross-functional teams to troubleshoot complex design and system-level issues.
• Develop scripts and automation using Python, Tcl, or similar languages to improve design and verification efficiency.
• Contribute to ASIC development from architecture and RTL through tapeout and silicon validation.

Skills

Verilog/SystemVerilog

DSP

RTL design

Digital design methodologies

Scripting (Python/Tcl)

Education

Bachelor’s or higher in Electrical Engineering, Computer Engineering, or related field

Tools

EDA tools

Python scripting

Tcl scripting

Job description

Celero Communications, Inc. in Irvine, CA is seeking a highly skilled ASIC Design Engineer to drive development of high-speed digital ASICs for optical communication systems.

The role focuses on Verilog/SystemVerilog, DSP and SerDes, RTL, and collaborating across Analog, Verification, and Physical Design to deliver tapeout-ready silicon. You will engage in synthesis, timing analysis, CDC, and PPA optimization, with scripting in Python or Tcl to automate flows; 5+ years in digital ASIC design