Senior ASIC DFT Architect for Multi-Block SOC

Blue Origin; Van Horn (TX); In loco; USD 269.000 - 377.000; Tempo pieno

Vantaggi offerti da questo lavoro

Medical insurance

Dental insurance

Vision insurance

401(k) match

Parental leave

Disability insurance

Stock options

Paid time off

Company holidays

Descrizione del lavoro

Blue Origin seeks a Principal ASIC DFT Designer for the ASIC Engineering SOC Team in the United States. You will own the test architecture for the TeraWave SOC program, defining strategies, implementing scan and built-in self-test, and delivering vectors for silicon bring-up and production testing.

The role requires senior technical leadership, collaboration with engineering teams, and responsibilities spanning from spec to silicon bring-up, including ATE pattern debug and defect analysis.

Competenze

• Bachelor's degree in Electrical Engineering, Computer Engineering, or related field.
• 10+ years in design for test for complex digital SOCs.

Mansioni

• Define DFT architecture and test strategy for large multi-block SOC designs.
• Author DFT specifications for scan, compression, boundary scan, and test access.
• Implement scan chain insertion, test clock control, and on-chip compression logic.
• Design built-in self-test for memories and logic.
• Generate and validate DFT vectors for silicon bring up and production test.
• Debug ATE pattern failures and collaborate with design and product teams.
• Support defect analysis and yield improvement using test data.
• Review test coverage and DFT timing with PD/verify teams.

Conoscenze

DFT architecture

ATPG patterns

DC/AC scan design

test vector generation

debug ATE patterns

test coverage analysis

Formazione

Bachelors in Electrical/Computer Engineering

Master's degree (preferred)

Strumenti

Tessent

DFTMAX

Modus

Descrizione del lavoro

Blue Origin seeks a Principal ASIC DFT Designer for the ASIC Engineering SOC Team in the United States. You will own the test architecture for the TeraWave SOC program, defining strategies, implementing scan and built-in self-test, and delivering vectors for silicon bring-up and production testing.

The role requires senior technical leadership, collaboration with engineering teams, and responsibilities spanning from spec to silicon bring-up, including ATE pattern debug and defect analysis.