Senior ASIC DFT Architect for Multi-Block SOC

Blue Origin; Seattle (WA); Sur place; USD 269 000 - 377 000; Plein temps

Avantages offerts par ce poste

Stock options

Paid time off

Education Support Program

Résumé du poste

Blue Origin is seeking a Principal ASIC DFT Designer on the ASIC Engineering SOC Team to own the test architecture for the TeraWave SOC program. You will define the DFT strategy for large multi-block designs, implement scan, compression, and on-chip test infrastructure, and deliver vectors for silicon bring up and production testing.

This is a senior individual contributor role spanning specification through silicon bring up, including ATE pattern debug and yield analysis, with collaboration

Qualifications

• Bachelor's degree in Electrical Engineering, Computer Engineering, or related technical field.
• 0
• Minimum 10 years of experience in design for test for complex digital SOCs.
• 0
• Experience defining DFT architecture and specifications for large multi-block SOC designs.
• 0
• Experience with DC and AC scan design and memory built in self test implementation.
• 0
• Experience generating ATPG patterns for automated test equipment and debugging ATE patterns.

Responsabilités

• Define DFT architecture and test strategy for large multi-block SOC designs.
• 0
• Author DFT specifications covering scan, compression, boundary scan, and test access mechanisms.
• 0
• Implement scan chain insertion, test clock control, and on chip compression logic.
• 0
• Design memory and logic built in self test infrastructure for embedded memories and logic.
• 0
• Generate and validate DFT vectors for silicon bring up and production test programs.
• 0
• Debug ATE pattern failures and drive resolution with design and product engineering teams.
• 0
• Support defect analysis and yield improvement using test coverage and silicon failure data.
• 0
• Review test coverage and DFT timing metrics with physical design and verification teams.

Connaissances

DFT design

Test infrastructure

ATPG pattern generation

Communication with stakeholders

Formation

Bachelor's degree in Electrical Engineering, Computer Engineering, or related technical field

Master's degree in Electrical Engineering, Computer Engineering, or related technical field

Outils

Tessent

DFTMAX

Modus

IEEE 1500/1687

Description du poste

Blue Origin is seeking a Principal ASIC DFT Designer on the ASIC Engineering SOC Team to own the test architecture for the TeraWave SOC program. You will define the DFT strategy for large multi-block designs, implement scan, compression, and on-chip test infrastructure, and deliver vectors for silicon bring up and production testing.

This is a senior individual contributor role spanning specification through silicon bring up, including ATE pattern debug and yield analysis, with collaboration