Senior SMTS: Silicon Design Engineer for ASICs

Advanced Micro Devices, Inc.

San Diego (CA)

On-site

USD 150,000 - 190,000

Full time

39 hours ago
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Job summary

AMD, Inc. is seeking SMTS Silicon Design Engineers in San Diego to research, design, develop, and test electronic components for semiconductor manufacturing.

You will lead ASIC design, verification, and documentation, and drive architecture, logic design, and system simulation efforts. Responsibilities include module interface definitions, complex IC layout collaboration, and evaluating design flows from high-level concepts to physical implementation.

Qualifications

  • Master’s degree in Computer/Electrical/Electronics Engineering or related field.
  • Four years of experience in a related engineering role.
  • Alternate: BS in related field plus six years of progressive experience.

Responsibilities

  • Lead ASIC development: definition, design, verification, documentation.
  • Architect and simulate logic and system level designs.
  • Define module interfaces/formats for simulation.
  • Lead multidimensional IC layout design efforts.
  • Evaluate flow from high-level design to synthesis, place & route, timing and power.
  • Collaborate with cross-functional teams on ASIC/layout design and issues.
  • Drive technically significant projects and processes.
  • Apply engineering principles to AMD product design, development, and testing.

Skills

Analog circuit design
Test plan development
Cadence Virtuoso
Electromigration analysis
Power/Perf optimization

Education

Master’s or foreign equivalent in Computer Engineering or Electrical/Electronics Engineering

Tools

Cadence Virtuoso tool
Ansys Totem
RedHawk

Job description

AMD, Inc. is seeking SMTS Silicon Design Engineers in San Diego to research, design, develop, and test electronic components for semiconductor manufacturing.

You will lead ASIC design, verification, and documentation, and drive architecture, logic design, and system simulation efforts. Responsibilities include module interface definitions, complex IC layout collaboration, and evaluating design flows from high-level concepts to physical implementation.

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