Senior ASIC Design Engineer – ML Chips & 2.5D Packaging

Amazon Inc.; Austin (TX); In loco; USD 203.000 - 215.000; Tempo pieno

Descrizione del lavoro

Annapurna Labs (U.S.) Inc. in Austin, TX seeks an experienced ASIC engineer to define, design and validate AWS next generation ML chips, cards and server integration.

You will work across HBM, memories and Serdes, coordinate with vendors, write tests, review designs, and participate in code reviews and cross-functional planning to deliver the next generation ML chip and its 2.5D packaging in a demanding AWS datacenter environment.

Competenze

• Master’s degree or foreign equivalent in Computer Science, Computer Engineering, Electronics Engineering, or a related field and 5 years of experience in the job offered or a related occupation.
• Bachelor’s degree or foreign equivalent in Computer Science, Computer Engineering, Electronics Engineering or a related field followed by 7 years of progressively responsible post-baccalaureate experience in the job offered or a related occupation.

Mansioni

• Participate in design and validation of AWS next generation ML chips, cards and server integration.
• Work with vendors, understand settings, write/modify tests, debug and collect data in the fleet.
• Participate in code review, design discussions, team planning, and ticket/metric/COE reviews.
• Collaborate with architects, design teams, software engineers to deliver the next generation ML chip.
• Responsible for IP integration, 2.5D design, bring up, characterization and validation.
• Focus on operational excellence, identify problems and propose solutions.

Conoscenze

SOC/IO/Subsystems

DDR/HBM

IP Integration

Formazione

Master’s degree in Computer Science/Computer Engineering/Electronics Engineering

Bachelor’s degree with 7+ years post-baccalaureate experience

Descrizione del lavoro

Annapurna Labs (U.S.) Inc. in Austin, TX seeks an experienced ASIC engineer to define, design and validate AWS next generation ML chips, cards and server integration.

You will work across HBM, memories and Serdes, coordinate with vendors, write tests, review designs, and participate in code reviews and cross-functional planning to deliver the next generation ML chip and its 2.5D packaging in a demanding AWS datacenter environment.