Senior ASIC Design Engineer — Lead, Verify & Optimize

Anysilicon; Minnesota; On-site; USD 90,000 - 130,000; Full time

Job summary

ForwardEdge ASIC LLC in Saint Paul, MN is seeking an experienced ASIC Design Engineer to lead and mentor a team of engineers in digital design blocks.

The role collaborates with architects to define digital and analog interfaces, develops detailed implementation plans, and creates verification test benches. Proficiency in RTL, HDLs, and scripting is essential for delivering robust designs.

Qualifications

• Bachelor’s or master’s degree in electrical or computer engineering.
• Minimum 3 years of experience as an ASIC Design Engineer.
• Proficiency in RTL coding languages and common scripting languages.
• Technical leadership experience is a plus.

Responsibilities

• Lead and mentor lower-level engineers in digital design blocks.
• Collaborate with architects to define and document digital/analog interfaces.
• Develop detailed implementation plans and specifications for complex design blocks.
• Create lower-level test bench code to verify functionality and features of design blocks.
• Develop test plans and coordinate with the Design Verification team for comprehensive verification.
• Synthesize RTL code using industry-standard tools and analyze results for optimization.
• Update RTL to meet Power, Performance, and Area (PPA) requirements.
• Execute plans for post-silicon lab validation.
• Support design blocks in a larger system-level environment through productization and production.
• Automate processes and methodologies using scripting languages (e.g., Python, Perl, Tcl).

Skills

ASIC design

FPGA design

RTL coding

HDL languages

Design verification

Mentoring

Education

Bachelor’s or master’s degree in electrical or computer engineering

Job description

ForwardEdge ASIC LLC in Saint Paul, MN is seeking an experienced ASIC Design Engineer to lead and mentor a team of engineers in digital design blocks.

The role collaborates with architects to define digital and analog interfaces, develops detailed implementation plans, and creates verification test benches. Proficiency in RTL, HDLs, and scripting is essential for delivering robust designs.